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@@ -1009,6 +1009,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
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uint64_t fb_location;
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uint32_t fb_format, fb_pitch_pixels, tiling_flags;
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u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
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+ u32 tmp;
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int r;
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/* no fb bound */
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@@ -1137,6 +1138,15 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
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WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
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(crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
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+ /* pageflip setup */
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+ /* make sure flip is at vb rather than hb */
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+ tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
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+ tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
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+ WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
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+
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+ /* set pageflip to happen anywhere in vblank interval */
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+ WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
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+
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if (!atomic && fb && fb != crtc->fb) {
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radeon_fb = to_radeon_framebuffer(fb);
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rbo = gem_to_radeon_bo(radeon_fb->obj);
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@@ -1167,6 +1177,7 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
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uint64_t fb_location;
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uint32_t fb_format, fb_pitch_pixels, tiling_flags;
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u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
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+ u32 tmp;
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int r;
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/* no fb bound */
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@@ -1294,6 +1305,15 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
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WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
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(crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
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+ /* pageflip setup */
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+ /* make sure flip is at vb rather than hb */
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+ tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
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+ tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
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+ WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
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+
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+ /* set pageflip to happen anywhere in vblank interval */
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+ WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
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+
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if (!atomic && fb && fb != crtc->fb) {
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radeon_fb = to_radeon_framebuffer(fb);
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rbo = gem_to_radeon_bo(radeon_fb->obj);
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