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@@ -145,14 +145,15 @@ lh7a40xuart_rx_chars (struct uart_port* port)
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{
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struct tty_struct* tty = port->info->tty;
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int cbRxMax = 256; /* (Gross) limit on receive */
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- unsigned int data, flag;/* Received data and status */
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+ unsigned int data; /* Received data and status */
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+ unsigned int flag;
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while (!(UR (port, UART_R_STATUS) & nRxRdy) && --cbRxMax) {
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data = UR (port, UART_R_DATA);
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flag = TTY_NORMAL;
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++port->icount.rx;
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- if (unlikely(data & RxError)) { /* Quick check, short-circuit */
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+ if (unlikely(data & RxError)) {
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if (data & RxBreak) {
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data &= ~(RxFramingError | RxParityError);
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++port->icount.brk;
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@@ -303,7 +304,7 @@ static void lh7a40xuart_set_mctrl (struct uart_port* port, unsigned int mctrl)
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/* Note, kernel appears to be setting DTR and RTS on console. */
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/* *** FIXME: this deserves more work. There's some work in
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- tracing all of the IO pins. */
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+ tracing all of the IO pins. */
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#if 0
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if( port->mapbase == UART1_PHYS) {
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gpioRegs_t *gpio = (gpioRegs_t *)IO_ADDRESS(GPIO_PHYS);
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@@ -662,9 +663,13 @@ static int __init lh7a40xuart_init(void)
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if (ret == 0) {
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int i;
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- for (i = 0; i < DEV_NR; i++)
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+ for (i = 0; i < DEV_NR; i++) {
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+ /* UART3, when used, requires GPIO pin reallocation */
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+ if (lh7a40x_ports[i].port.mapbase == UART3_PHYS)
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+ GPIO_PINMUX |= 1<<3;
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uart_add_one_port (&lh7a40x_reg,
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&lh7a40x_ports[i].port);
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+ }
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}
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return ret;
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}
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