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@@ -111,16 +111,59 @@ static void davinci_mcbsp_start(struct snd_pcm_substream *substream)
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{
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
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struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
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+ struct snd_soc_device *socdev = rtd->socdev;
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+ struct snd_soc_platform *platform = socdev->platform;
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u32 w;
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u32 w;
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+ int ret;
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/* Start the sample generator and enable transmitter/receiver */
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/* Start the sample generator and enable transmitter/receiver */
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w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
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w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
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MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST, 1);
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MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST, 1);
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- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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+ davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
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+
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+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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+ /* Stop the DMA to avoid data loss */
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+ /* while the transmitter is out of reset to handle XSYNCERR */
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+ if (platform->pcm_ops->trigger) {
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+ ret = platform->pcm_ops->trigger(substream,
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+ SNDRV_PCM_TRIGGER_STOP);
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+ if (ret < 0)
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+ printk(KERN_DEBUG "Playback DMA stop failed\n");
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+ }
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+
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+ /* Enable the transmitter */
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+ w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
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MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
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MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
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- else
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+ davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
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+
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+ /* wait for any unexpected frame sync error to occur */
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+ udelay(100);
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+
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+ /* Disable the transmitter to clear any outstanding XSYNCERR */
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+ w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
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+ MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
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+ davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
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+
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+ /* Restart the DMA */
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+ if (platform->pcm_ops->trigger) {
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+ ret = platform->pcm_ops->trigger(substream,
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+ SNDRV_PCM_TRIGGER_START);
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+ if (ret < 0)
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+ printk(KERN_DEBUG "Playback DMA start failed\n");
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+ }
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+ /* Enable the transmitter */
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+ w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
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+ MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
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+ davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
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+
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+ } else {
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+
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+ /* Enable the reciever */
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+ w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
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MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 1);
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MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 1);
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- davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
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+ davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
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+ }
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+
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/* Start frame sync */
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/* Start frame sync */
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w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
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w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
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