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@@ -40,6 +40,12 @@
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#define TLB_V6_I_ASID (1 << 18)
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#define TLB_BTB (1 << 28)
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+
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+/* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */
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+#define TLB_V7_UIS_PAGE (1 << 19)
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+#define TLB_V7_UIS_FULL (1 << 20)
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+#define TLB_V7_UIS_ASID (1 << 21)
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+
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#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */
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#define TLB_DCLEAN (1 << 30)
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#define TLB_WB (1 << 31)
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@@ -176,9 +182,17 @@
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# define v6wbi_always_flags (-1UL)
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#endif
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+#ifdef CONFIG_SMP
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+#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
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+ TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
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+#else
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+#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
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+ TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
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+#endif
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+
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#ifdef CONFIG_CPU_TLB_V7
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-# define v7wbi_possible_flags v6wbi_tlb_flags
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-# define v7wbi_always_flags v6wbi_tlb_flags
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+# define v7wbi_possible_flags v7wbi_tlb_flags
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+# define v7wbi_always_flags v7wbi_tlb_flags
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# ifdef _TLB
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# define MULTI_TLB 1
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# else
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@@ -316,6 +330,8 @@ static inline void local_flush_tlb_all(void)
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asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
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if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
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asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
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+ if (tlb_flag(TLB_V7_UIS_FULL))
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+ asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc");
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if (tlb_flag(TLB_BTB)) {
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/* flush the branch target cache */
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@@ -351,6 +367,8 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
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asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
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if (tlb_flag(TLB_V6_I_ASID))
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asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
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+ if (tlb_flag(TLB_V7_UIS_ASID))
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+ asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc");
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if (tlb_flag(TLB_BTB)) {
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/* flush the branch target cache */
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@@ -389,6 +407,8 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
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asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
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if (tlb_flag(TLB_V6_I_PAGE))
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asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
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+ if (tlb_flag(TLB_V7_UIS_PAGE))
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+ asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc");
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if (tlb_flag(TLB_BTB)) {
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/* flush the branch target cache */
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@@ -424,6 +444,8 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
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asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
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if (tlb_flag(TLB_V6_I_PAGE))
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asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
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+ if (tlb_flag(TLB_V7_UIS_PAGE))
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+ asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (kaddr) : "cc");
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if (tlb_flag(TLB_BTB)) {
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/* flush the branch target cache */
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