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@@ -149,7 +149,7 @@ struct tmds_config {
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};
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static const struct tmds_config tegra2_tmds_config[] = {
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- { /* 480p modes */
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+ { /* slow pixel clock modes */
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.pclk = 27000000,
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.pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
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SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
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@@ -163,21 +163,8 @@ static const struct tmds_config tegra2_tmds_config[] = {
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DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
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DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
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DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
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- }, { /* 720p modes */
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- .pclk = 74250000,
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- .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
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- SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
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- SOR_PLL_TX_REG_LOAD(3),
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- .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
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- .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
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- PE_CURRENT1(PE_CURRENT_6_0_mA) |
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- PE_CURRENT2(PE_CURRENT_6_0_mA) |
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- PE_CURRENT3(PE_CURRENT_6_0_mA),
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- .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
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- DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
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- DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
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- DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
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- }, { /* 1080p modes */
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+ },
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+ { /* high pixel clock modes */
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.pclk = UINT_MAX,
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.pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
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SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
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