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@@ -43,7 +43,7 @@
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#define WL18XX_RX_CHECKSUM_MASK 0x40
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-static char *ht_mode_param = "wide";
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+static char *ht_mode_param = "default";
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static char *board_type_param = "hdk";
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static bool checksum_param = false;
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static bool enable_11a_param = true;
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@@ -1286,34 +1286,6 @@ static int __devinit wl18xx_probe(struct platform_device *pdev)
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if (num_rx_desc_param != -1)
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wl->num_rx_desc = num_rx_desc_param;
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- if (!strcmp(ht_mode_param, "wide")) {
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- memcpy(&wl->ht_cap[IEEE80211_BAND_2GHZ],
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- &wl18xx_siso40_ht_cap,
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- sizeof(wl18xx_siso40_ht_cap));
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- memcpy(&wl->ht_cap[IEEE80211_BAND_5GHZ],
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- &wl18xx_siso40_ht_cap,
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- sizeof(wl18xx_siso40_ht_cap));
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- } else if (!strcmp(ht_mode_param, "mimo")) {
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- memcpy(&wl->ht_cap[IEEE80211_BAND_2GHZ],
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- &wl18xx_mimo_ht_cap_2ghz,
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- sizeof(wl18xx_mimo_ht_cap_2ghz));
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- /* we don't support MIMO in 5Ghz */
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- memcpy(&wl->ht_cap[IEEE80211_BAND_5GHZ],
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- &wl18xx_siso20_ht_cap,
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- sizeof(wl18xx_siso20_ht_cap));
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- } else if (!strcmp(ht_mode_param, "siso20")) {
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- memcpy(&wl->ht_cap[IEEE80211_BAND_2GHZ],
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- &wl18xx_siso20_ht_cap,
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- sizeof(wl18xx_siso20_ht_cap));
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- memcpy(&wl->ht_cap[IEEE80211_BAND_5GHZ],
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- &wl18xx_siso20_ht_cap,
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- sizeof(wl18xx_siso20_ht_cap));
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- } else {
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- wl1271_error("invalid ht_mode '%s'", ht_mode_param);
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- ret = -EINVAL;
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- goto out_free;
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- }
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-
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ret = wl18xx_conf_init(wl, &pdev->dev);
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if (ret < 0)
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goto out_free;
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@@ -1359,6 +1331,37 @@ static int __devinit wl18xx_probe(struct platform_device *pdev)
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if (dc2dc_param != -1)
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priv->conf.phy.external_pa_dc2dc = dc2dc_param;
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+ if (!strcmp(ht_mode_param, "default")) {
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+ /*
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+ * Only support mimo with multiple antennas. Fall back to
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+ * siso20.
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+ */
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+ if (priv->conf.phy.number_of_assembled_ant2_4 >= 2)
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+ wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
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+ &wl18xx_mimo_ht_cap_2ghz);
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+ else
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+ wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
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+ &wl18xx_siso20_ht_cap);
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+
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+ /* 5Ghz is always wide */
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+ wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
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+ &wl18xx_siso40_ht_cap);
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+ } else if (!strcmp(ht_mode_param, "wide")) {
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+ wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
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+ &wl18xx_siso40_ht_cap);
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+ wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
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+ &wl18xx_siso40_ht_cap);
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+ } else if (!strcmp(ht_mode_param, "siso20")) {
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+ wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
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+ &wl18xx_siso20_ht_cap);
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+ wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
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+ &wl18xx_siso20_ht_cap);
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+ } else {
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+ wl1271_error("invalid ht_mode '%s'", ht_mode_param);
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+ ret = -EINVAL;
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+ goto out_free;
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+ }
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+
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if (!checksum_param) {
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wl18xx_ops.set_rx_csum = NULL;
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wl18xx_ops.init_vif = NULL;
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@@ -1403,7 +1406,7 @@ static void __exit wl18xx_exit(void)
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module_exit(wl18xx_exit);
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module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR);
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-MODULE_PARM_DESC(ht_mode, "Force HT mode: wide (default), mimo or siso20");
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+MODULE_PARM_DESC(ht_mode, "Force HT mode: wide or siso20");
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module_param_named(board_type, board_type_param, charp, S_IRUSR);
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MODULE_PARM_DESC(board_type, "Board type: fpga, hdk (default), evb, com8 or "
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