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+#ifndef _ASM_POWERPC_EXCEPTION_H
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+#define _ASM_POWERPC_EXCEPTION_H
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+/*
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+ * Extracted from head_64.S
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+ *
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+ * PowerPC version
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+ * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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+ *
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+ * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
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+ * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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+ * Adapted for Power Macintosh by Paul Mackerras.
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+ * Low-level exception handlers and MMU support
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+ * rewritten by Paul Mackerras.
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+ * Copyright (C) 1996 Paul Mackerras.
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+ *
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+ * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
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+ * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
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+ *
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+ * This file contains the low-level support and setup for the
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+ * PowerPC-64 platform, including trap and interrupt dispatch.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License
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+ * as published by the Free Software Foundation; either version
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+ * 2 of the License, or (at your option) any later version.
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+ */
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+/*
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+ * The following macros define the code that appears as
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+ * the prologue to each of the exception handlers. They
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+ * are split into two parts to allow a single kernel binary
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+ * to be used for pSeries and iSeries.
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+ *
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+ * We make as much of the exception code common between native
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+ * exception handlers (including pSeries LPAR) and iSeries LPAR
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+ * implementations as possible.
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+ */
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+
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+#define EX_R9 0
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+#define EX_R10 8
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+#define EX_R11 16
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+#define EX_R12 24
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+#define EX_R13 32
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+#define EX_SRR0 40
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+#define EX_DAR 48
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+#define EX_DSISR 56
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+#define EX_CCR 60
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+#define EX_R3 64
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+#define EX_LR 72
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+
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+/*
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+ * We're short on space and time in the exception prolog, so we can't
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+ * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
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+ * low halfword of the address, but for Kdump we need the whole low
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+ * word.
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+ */
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+#ifdef CONFIG_CRASH_DUMP
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+#define LOAD_HANDLER(reg, label) \
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+ oris reg,reg,(label)@h; /* virt addr of handler ... */ \
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+ ori reg,reg,(label)@l; /* .. and the rest */
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+#else
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+#define LOAD_HANDLER(reg, label) \
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+ ori reg,reg,(label)@l; /* virt addr of handler ... */
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+#endif
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+
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+/*
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+ * Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode.
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+ * The firmware calls the registered system_reset_fwnmi and
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+ * machine_check_fwnmi handlers in 32bit mode if the cpu happens to run
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+ * a 32bit application at the time of the event.
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+ * This firmware bug is present on POWER4 and JS20.
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+ */
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+#define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label) \
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+ mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
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+ std r9,area+EX_R9(r13); /* save r9 - r12 */ \
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+ std r10,area+EX_R10(r13); \
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+ std r11,area+EX_R11(r13); \
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+ std r12,area+EX_R12(r13); \
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+ mfspr r9,SPRN_SPRG1; \
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+ std r9,area+EX_R13(r13); \
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+ mfcr r9; \
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+ clrrdi r12,r13,32; /* get high part of &label */ \
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+ mfmsr r10; \
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+ /* force 64bit mode */ \
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+ li r11,5; /* MSR_SF_LG|MSR_ISF_LG */ \
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+ rldimi r10,r11,61,0; /* insert into top 3 bits */ \
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+ /* done 64bit mode */ \
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+ mfspr r11,SPRN_SRR0; /* save SRR0 */ \
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+ LOAD_HANDLER(r12,label) \
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+ ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
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+ mtspr SPRN_SRR0,r12; \
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+ mfspr r12,SPRN_SRR1; /* and SRR1 */ \
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+ mtspr SPRN_SRR1,r10; \
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+ rfid; \
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+ b . /* prevent speculative execution */
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+
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+#define EXCEPTION_PROLOG_PSERIES(area, label) \
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+ mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
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+ std r9,area+EX_R9(r13); /* save r9 - r12 */ \
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+ std r10,area+EX_R10(r13); \
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+ std r11,area+EX_R11(r13); \
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+ std r12,area+EX_R12(r13); \
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+ mfspr r9,SPRN_SPRG1; \
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+ std r9,area+EX_R13(r13); \
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+ mfcr r9; \
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+ clrrdi r12,r13,32; /* get high part of &label */ \
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+ mfmsr r10; \
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+ mfspr r11,SPRN_SRR0; /* save SRR0 */ \
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+ LOAD_HANDLER(r12,label) \
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+ ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
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+ mtspr SPRN_SRR0,r12; \
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+ mfspr r12,SPRN_SRR1; /* and SRR1 */ \
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+ mtspr SPRN_SRR1,r10; \
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+ rfid; \
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+ b . /* prevent speculative execution */
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+
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+/*
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+ * This is the start of the interrupt handlers for iSeries
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+ * This code runs with relocation on.
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+ */
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+#define EXCEPTION_PROLOG_ISERIES_1(area) \
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+ mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
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+ std r9,area+EX_R9(r13); /* save r9 - r12 */ \
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+ std r10,area+EX_R10(r13); \
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+ std r11,area+EX_R11(r13); \
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+ std r12,area+EX_R12(r13); \
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+ mfspr r9,SPRN_SPRG1; \
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+ std r9,area+EX_R13(r13); \
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+ mfcr r9
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+
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+#define EXCEPTION_PROLOG_ISERIES_2 \
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+ mfmsr r10; \
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+ ld r12,PACALPPACAPTR(r13); \
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+ ld r11,LPPACASRR0(r12); \
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+ ld r12,LPPACASRR1(r12); \
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+ ori r10,r10,MSR_RI; \
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+ mtmsrd r10,1
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+
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+/*
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+ * The common exception prolog is used for all except a few exceptions
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+ * such as a segment miss on a kernel address. We have to be prepared
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+ * to take another exception from the point where we first touch the
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+ * kernel stack onwards.
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+ *
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+ * On entry r13 points to the paca, r9-r13 are saved in the paca,
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+ * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
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+ * SRR1, and relocation is on.
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+ */
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+#define EXCEPTION_PROLOG_COMMON(n, area) \
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+ andi. r10,r12,MSR_PR; /* See if coming from user */ \
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+ mr r10,r1; /* Save r1 */ \
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+ subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
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+ beq- 1f; \
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+ ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
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+1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
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+ bge- cr1,2f; /* abort if it is */ \
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+ b 3f; \
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+2: li r1,(n); /* will be reloaded later */ \
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+ sth r1,PACA_TRAP_SAVE(r13); \
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+ b bad_stack; \
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+3: std r9,_CCR(r1); /* save CR in stackframe */ \
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+ std r11,_NIP(r1); /* save SRR0 in stackframe */ \
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+ std r12,_MSR(r1); /* save SRR1 in stackframe */ \
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+ std r10,0(r1); /* make stack chain pointer */ \
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+ std r0,GPR0(r1); /* save r0 in stackframe */ \
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+ std r10,GPR1(r1); /* save r1 in stackframe */ \
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+ ACCOUNT_CPU_USER_ENTRY(r9, r10); \
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+ std r2,GPR2(r1); /* save r2 in stackframe */ \
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+ SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
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+ SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
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+ ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
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+ ld r10,area+EX_R10(r13); \
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+ std r9,GPR9(r1); \
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+ std r10,GPR10(r1); \
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+ ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
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+ ld r10,area+EX_R12(r13); \
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+ ld r11,area+EX_R13(r13); \
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+ std r9,GPR11(r1); \
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+ std r10,GPR12(r1); \
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+ std r11,GPR13(r1); \
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+ ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
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+ mflr r9; /* save LR in stackframe */ \
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+ std r9,_LINK(r1); \
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+ mfctr r10; /* save CTR in stackframe */ \
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+ std r10,_CTR(r1); \
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+ lbz r10,PACASOFTIRQEN(r13); \
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+ mfspr r11,SPRN_XER; /* save XER in stackframe */ \
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+ std r10,SOFTE(r1); \
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+ std r11,_XER(r1); \
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+ li r9,(n)+1; \
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+ std r9,_TRAP(r1); /* set trap number */ \
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+ li r10,0; \
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+ ld r11,exception_marker@toc(r2); \
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+ std r10,RESULT(r1); /* clear regs->result */ \
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+ std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
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+
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+/*
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+ * Exception vectors.
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+ */
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+#define STD_EXCEPTION_PSERIES(n, label) \
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+ . = n; \
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+ .globl label##_pSeries; \
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+label##_pSeries: \
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+ HMT_MEDIUM; \
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+ mtspr SPRN_SPRG1,r13; /* save r13 */ \
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+ EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
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+
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+#define HSTD_EXCEPTION_PSERIES(n, label) \
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+ . = n; \
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+ .globl label##_pSeries; \
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+label##_pSeries: \
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+ HMT_MEDIUM; \
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+ mtspr SPRN_SPRG1,r20; /* save r20 */ \
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+ mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \
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+ mtspr SPRN_SRR0,r20; \
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+ mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \
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+ mtspr SPRN_SRR1,r20; \
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+ mfspr r20,SPRN_SPRG1; /* restore r20 */ \
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+ mtspr SPRN_SPRG1,r13; /* save r13 */ \
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+ EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
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+
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+
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+#define MASKABLE_EXCEPTION_PSERIES(n, label) \
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+ . = n; \
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+ .globl label##_pSeries; \
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+label##_pSeries: \
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+ HMT_MEDIUM; \
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+ mtspr SPRN_SPRG1,r13; /* save r13 */ \
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+ mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
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+ std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \
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+ std r10,PACA_EXGEN+EX_R10(r13); \
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+ lbz r10,PACASOFTIRQEN(r13); \
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+ mfcr r9; \
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+ cmpwi r10,0; \
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+ beq masked_interrupt; \
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+ mfspr r10,SPRN_SPRG1; \
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+ std r10,PACA_EXGEN+EX_R13(r13); \
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+ std r11,PACA_EXGEN+EX_R11(r13); \
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+ std r12,PACA_EXGEN+EX_R12(r13); \
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+ clrrdi r12,r13,32; /* get high part of &label */ \
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+ mfmsr r10; \
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+ mfspr r11,SPRN_SRR0; /* save SRR0 */ \
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+ LOAD_HANDLER(r12,label##_common) \
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+ ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
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+ mtspr SPRN_SRR0,r12; \
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+ mfspr r12,SPRN_SRR1; /* and SRR1 */ \
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+ mtspr SPRN_SRR1,r10; \
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+ rfid; \
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+ b . /* prevent speculative execution */
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+
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+#define STD_EXCEPTION_ISERIES(n, label, area) \
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+ .globl label##_iSeries; \
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+label##_iSeries: \
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+ HMT_MEDIUM; \
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+ mtspr SPRN_SPRG1,r13; /* save r13 */ \
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+ EXCEPTION_PROLOG_ISERIES_1(area); \
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+ EXCEPTION_PROLOG_ISERIES_2; \
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+ b label##_common
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+
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+#define MASKABLE_EXCEPTION_ISERIES(n, label) \
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+ .globl label##_iSeries; \
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+label##_iSeries: \
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+ HMT_MEDIUM; \
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+ mtspr SPRN_SPRG1,r13; /* save r13 */ \
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+ EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
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+ lbz r10,PACASOFTIRQEN(r13); \
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+ cmpwi 0,r10,0; \
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+ beq- label##_iSeries_masked; \
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+ EXCEPTION_PROLOG_ISERIES_2; \
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+ b label##_common; \
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+
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+#ifdef CONFIG_PPC_ISERIES
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+#define DISABLE_INTS \
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+ li r11,0; \
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+ stb r11,PACASOFTIRQEN(r13); \
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+BEGIN_FW_FTR_SECTION; \
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+ stb r11,PACAHARDIRQEN(r13); \
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+END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \
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+BEGIN_FW_FTR_SECTION; \
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+ mfmsr r10; \
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+ ori r10,r10,MSR_EE; \
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+ mtmsrd r10,1; \
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+END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
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+
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+#else
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+#define DISABLE_INTS \
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+ li r11,0; \
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+ stb r11,PACASOFTIRQEN(r13); \
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+ stb r11,PACAHARDIRQEN(r13)
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+
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+#endif /* CONFIG_PPC_ISERIES */
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+
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+#define ENABLE_INTS \
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+ ld r12,_MSR(r1); \
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+ mfmsr r11; \
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+ rlwimi r11,r12,0,MSR_EE; \
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+ mtmsrd r11,1
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+
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+#define STD_EXCEPTION_COMMON(trap, label, hdlr) \
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+ .align 7; \
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+ .globl label##_common; \
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+label##_common: \
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+ EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
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+ DISABLE_INTS; \
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+ bl .save_nvgprs; \
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+ addi r3,r1,STACK_FRAME_OVERHEAD; \
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+ bl hdlr; \
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+ b .ret_from_except
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+
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+/*
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+ * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
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+ * in the idle task and therefore need the special idle handling.
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+ */
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+#define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr) \
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+ .align 7; \
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+ .globl label##_common; \
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+label##_common: \
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+ EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
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+ FINISH_NAP; \
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+ DISABLE_INTS; \
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+ bl .save_nvgprs; \
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+ addi r3,r1,STACK_FRAME_OVERHEAD; \
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+ bl hdlr; \
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+ b .ret_from_except
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+
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+#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
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+ .align 7; \
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+ .globl label##_common; \
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+label##_common: \
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+ EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
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+ FINISH_NAP; \
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+ DISABLE_INTS; \
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+ bl .ppc64_runlatch_on; \
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+ addi r3,r1,STACK_FRAME_OVERHEAD; \
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+ bl hdlr; \
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+ b .ret_from_except_lite
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+
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+/*
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+ * When the idle code in power4_idle puts the CPU into NAP mode,
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+ * it has to do so in a loop, and relies on the external interrupt
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+ * and decrementer interrupt entry code to get it out of the loop.
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+ * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
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+ * to signal that it is in the loop and needs help to get out.
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+ */
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+#ifdef CONFIG_PPC_970_NAP
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+#define FINISH_NAP \
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+BEGIN_FTR_SECTION \
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+ clrrdi r11,r1,THREAD_SHIFT; \
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+ ld r9,TI_LOCAL_FLAGS(r11); \
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+ andi. r10,r9,_TLF_NAPPING; \
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+ bnel power4_fixup_nap; \
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+END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
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+#else
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+#define FINISH_NAP
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+#endif
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+
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+#endif /* _ASM_POWERPC_EXCEPTION_H */
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Stephen Rothwell