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@@ -4,12 +4,12 @@
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compatible = "nvidia,tegra20";
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interrupt-parent = <&intc>;
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- pmc@7000f400 {
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+ pmc {
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compatible = "nvidia,tegra20-pmc";
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reg = <0x7000e400 0x400>;
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};
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- intc: interrupt-controller@50041000 {
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+ intc: interrupt-controller {
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compatible = "arm,cortex-a9-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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@@ -23,7 +23,7 @@
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0 57 0x04>;
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};
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- apbdma: dma@6000a000 {
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+ apbdma: dma {
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compatible = "nvidia,tegra20-apbdma";
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reg = <0x6000a000 0x1200>;
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interrupts = <0 104 0x04
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@@ -90,12 +90,12 @@
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nvidia,dma-request-selector = <&apbdma 1>;
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};
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- das@70000c00 {
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+ das {
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compatible = "nvidia,tegra20-das";
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reg = <0x70000c00 0x80>;
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};
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- gpio: gpio@6000d000 {
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+ gpio: gpio {
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compatible = "nvidia,tegra20-gpio";
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reg = <0x6000d000 0x1000>;
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interrupts = <0 32 0x04
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@@ -111,7 +111,7 @@
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interrupt-controller;
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};
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- pinmux: pinmux@70000000 {
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+ pinmux: pinmux {
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compatible = "nvidia,tegra20-pinmux";
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reg = <0x70000014 0x10 /* Tri-state registers */
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0x70000080 0x20 /* Mux registers */
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@@ -154,7 +154,7 @@
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interrupts = <0 91 0x04>;
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};
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- emc@7000f400 {
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+ emc {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-emc";
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@@ -207,7 +207,7 @@
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phy_type = "utmi";
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};
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- ahb: ahb@6000c004 {
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+ ahb {
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compatible = "nvidia,tegra20-ahb";
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reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
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};
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