|
@@ -29,6 +29,7 @@
|
|
#include <asm/mmu.h>
|
|
#include <asm/mmu.h>
|
|
#include <asm/ppc_sys.h>
|
|
#include <asm/ppc_sys.h>
|
|
#include <asm/kgdb.h>
|
|
#include <asm/kgdb.h>
|
|
|
|
+#include <asm/delay.h>
|
|
|
|
|
|
#include <syslib/ppc83xx_setup.h>
|
|
#include <syslib/ppc83xx_setup.h>
|
|
|
|
|
|
@@ -117,7 +118,34 @@ mpc83xx_early_serial_map(void)
|
|
void
|
|
void
|
|
mpc83xx_restart(char *cmd)
|
|
mpc83xx_restart(char *cmd)
|
|
{
|
|
{
|
|
|
|
+ volatile unsigned char __iomem *reg;
|
|
|
|
+ unsigned char tmp;
|
|
|
|
+
|
|
|
|
+ reg = ioremap(BCSR_PHYS_ADDR, BCSR_SIZE);
|
|
|
|
+
|
|
local_irq_disable();
|
|
local_irq_disable();
|
|
|
|
+
|
|
|
|
+ /*
|
|
|
|
+ * Unlock the BCSR bits so a PRST will update the contents.
|
|
|
|
+ * Otherwise the reset asserts but doesn't clear.
|
|
|
|
+ */
|
|
|
|
+ tmp = in_8(reg + BCSR_MISC_REG3_OFF);
|
|
|
|
+ tmp |= BCSR_MISC_REG3_CNFLOCK; /* low true, high false */
|
|
|
|
+ out_8(reg + BCSR_MISC_REG3_OFF, tmp);
|
|
|
|
+
|
|
|
|
+ /*
|
|
|
|
+ * Trigger a reset via a low->high transition of the
|
|
|
|
+ * PORESET bit.
|
|
|
|
+ */
|
|
|
|
+ tmp = in_8(reg + BCSR_MISC_REG2_OFF);
|
|
|
|
+ tmp &= ~BCSR_MISC_REG2_PORESET;
|
|
|
|
+ out_8(reg + BCSR_MISC_REG2_OFF, tmp);
|
|
|
|
+
|
|
|
|
+ udelay(1);
|
|
|
|
+
|
|
|
|
+ tmp |= BCSR_MISC_REG2_PORESET;
|
|
|
|
+ out_8(reg + BCSR_MISC_REG2_OFF, tmp);
|
|
|
|
+
|
|
for(;;);
|
|
for(;;);
|
|
}
|
|
}
|
|
|
|
|