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@@ -30,16 +30,92 @@ static struct clk clk_sclk_hdmi27m = {
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.rate = 27000000,
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};
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+static struct clk clk_sclk_hdmiphy = {
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+ .name = "sclk_hdmiphy",
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+ .id = -1,
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+};
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+
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+static struct clk clk_sclk_usbphy0 = {
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+ .name = "sclk_usbphy0",
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+ .id = -1,
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+ .rate = 27000000,
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+};
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+
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+static struct clk clk_sclk_usbphy1 = {
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+ .name = "sclk_usbphy1",
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+ .id = -1,
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+};
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+
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+static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable)
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+{
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+ return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
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+}
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+
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+static int s5pv310_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
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+{
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+ return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
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+}
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+
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+static int s5pv310_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
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+{
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+ return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
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+}
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+
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+static int s5pv310_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
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+{
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+ return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
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+}
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+
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+static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
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+{
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+ return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
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+}
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+
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static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
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}
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+static int s5pv310_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
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+{
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+ return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
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+}
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+
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+static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable)
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+{
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+ return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
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+}
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+
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+static int s5pv310_clk_ip_image_ctrl(struct clk *clk, int enable)
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+{
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+ return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
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+}
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+
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+static int s5pv310_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
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+{
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+ return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
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+}
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+
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+static int s5pv310_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
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+{
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+ return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
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+}
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+
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+static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable)
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+{
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+ return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
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+}
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+
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static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
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}
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+static int s5pv310_clk_ip_perir_ctrl(struct clk *clk, int enable)
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+{
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+ return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
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+}
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+
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/* Core list of CMU_CPU side */
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static struct clksrc_clk clk_mout_apll = {
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@@ -79,7 +155,7 @@ static struct clksrc_clk clk_mout_mpll = {
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};
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static struct clk *clkset_moutcore_list[] = {
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- [0] = &clk_sclk_apll.clk,
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+ [0] = &clk_mout_apll.clk,
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[1] = &clk_mout_mpll.clk,
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};
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@@ -150,24 +226,6 @@ static struct clksrc_clk clk_periphclk = {
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.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
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};
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-static struct clksrc_clk clk_atclk = {
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- .clk = {
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- .name = "atclk",
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- .id = -1,
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- .parent = &clk_moutcore.clk,
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- },
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- .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 16, .size = 3 },
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-};
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-
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-static struct clksrc_clk clk_pclk_dbg = {
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- .clk = {
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- .name = "pclk_dbg",
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- .id = -1,
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- .parent = &clk_atclk.clk,
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- },
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- .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 20, .size = 3 },
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-};
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-
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/* Core list of CMU_CORE side */
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static struct clk *clkset_corebus_list[] = {
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@@ -241,7 +299,7 @@ static struct clk *clkset_aclk_top_list[] = {
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[1] = &clk_sclk_apll.clk,
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};
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-static struct clksrc_sources clkset_aclk_200 = {
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+static struct clksrc_sources clkset_aclk = {
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.sources = clkset_aclk_top_list,
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.nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
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};
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@@ -251,52 +309,37 @@ static struct clksrc_clk clk_aclk_200 = {
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.name = "aclk_200",
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.id = -1,
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},
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- .sources = &clkset_aclk_200,
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+ .sources = &clkset_aclk,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
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.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
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};
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-static struct clksrc_sources clkset_aclk_100 = {
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- .sources = clkset_aclk_top_list,
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- .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
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-};
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-
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static struct clksrc_clk clk_aclk_100 = {
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.clk = {
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.name = "aclk_100",
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.id = -1,
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},
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- .sources = &clkset_aclk_100,
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+ .sources = &clkset_aclk,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
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.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
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};
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-static struct clksrc_sources clkset_aclk_160 = {
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- .sources = clkset_aclk_top_list,
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- .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
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-};
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-
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static struct clksrc_clk clk_aclk_160 = {
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.clk = {
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.name = "aclk_160",
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.id = -1,
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},
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- .sources = &clkset_aclk_160,
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+ .sources = &clkset_aclk,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
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.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
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};
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-static struct clksrc_sources clkset_aclk_133 = {
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- .sources = clkset_aclk_top_list,
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- .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
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-};
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-
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static struct clksrc_clk clk_aclk_133 = {
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.clk = {
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.name = "aclk_133",
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.id = -1,
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},
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- .sources = &clkset_aclk_133,
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+ .sources = &clkset_aclk,
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.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
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.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
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};
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@@ -315,6 +358,8 @@ static struct clksrc_clk clk_vpllsrc = {
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.clk = {
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.name = "vpll_src",
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.id = -1,
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+ .enable = s5pv310_clksrc_mask_top_ctrl,
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+ .ctrlbit = (1 << 0),
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},
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.sources = &clkset_vpllsrc,
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.reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
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@@ -346,7 +391,175 @@ static struct clk init_clocks_disable[] = {
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.parent = &clk_aclk_100.clk,
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.enable = s5pv310_clk_ip_peril_ctrl,
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.ctrlbit = (1<<24),
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- }
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+ }, {
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+ .name = "csis",
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+ .id = 0,
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+ .enable = s5pv310_clk_ip_cam_ctrl,
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+ .ctrlbit = (1 << 4),
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+ }, {
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+ .name = "csis",
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+ .id = 1,
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+ .enable = s5pv310_clk_ip_cam_ctrl,
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+ .ctrlbit = (1 << 5),
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+ }, {
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+ .name = "fimc",
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+ .id = 0,
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+ .enable = s5pv310_clk_ip_cam_ctrl,
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+ .ctrlbit = (1 << 0),
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+ }, {
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+ .name = "fimc",
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+ .id = 1,
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+ .enable = s5pv310_clk_ip_cam_ctrl,
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+ .ctrlbit = (1 << 1),
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+ }, {
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+ .name = "fimc",
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+ .id = 2,
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+ .enable = s5pv310_clk_ip_cam_ctrl,
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+ .ctrlbit = (1 << 2),
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+ }, {
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+ .name = "fimc",
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+ .id = 3,
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+ .enable = s5pv310_clk_ip_cam_ctrl,
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+ .ctrlbit = (1 << 3),
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+ }, {
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+ .name = "fimd",
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+ .id = 0,
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+ .enable = s5pv310_clk_ip_lcd0_ctrl,
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+ .ctrlbit = (1 << 0),
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+ }, {
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+ .name = "fimd",
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+ .id = 1,
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+ .enable = s5pv310_clk_ip_lcd1_ctrl,
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+ .ctrlbit = (1 << 0),
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+ }, {
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+ .name = "hsmmc",
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+ .id = 0,
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+ .parent = &clk_aclk_133.clk,
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+ .enable = s5pv310_clk_ip_fsys_ctrl,
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+ .ctrlbit = (1 << 5),
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+ }, {
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+ .name = "hsmmc",
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+ .id = 1,
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+ .parent = &clk_aclk_133.clk,
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+ .enable = s5pv310_clk_ip_fsys_ctrl,
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+ .ctrlbit = (1 << 6),
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+ }, {
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+ .name = "hsmmc",
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+ .id = 2,
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+ .parent = &clk_aclk_133.clk,
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+ .enable = s5pv310_clk_ip_fsys_ctrl,
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+ .ctrlbit = (1 << 7),
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+ }, {
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+ .name = "hsmmc",
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+ .id = 3,
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+ .parent = &clk_aclk_133.clk,
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+ .enable = s5pv310_clk_ip_fsys_ctrl,
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+ .ctrlbit = (1 << 8),
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+ }, {
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+ .name = "hsmmc",
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+ .id = 4,
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+ .parent = &clk_aclk_133.clk,
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+ .enable = s5pv310_clk_ip_fsys_ctrl,
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+ .ctrlbit = (1 << 9),
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+ }, {
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+ .name = "sata",
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+ .id = -1,
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+ .enable = s5pv310_clk_ip_fsys_ctrl,
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+ .ctrlbit = (1 << 10),
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+ }, {
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+ .name = "adc",
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+ .id = -1,
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+ .enable = s5pv310_clk_ip_peril_ctrl,
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+ .ctrlbit = (1 << 15),
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+ }, {
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+ .name = "rtc",
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+ .id = -1,
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+ .enable = s5pv310_clk_ip_perir_ctrl,
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+ .ctrlbit = (1 << 15),
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+ }, {
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+ .name = "watchdog",
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+ .id = -1,
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+ .enable = s5pv310_clk_ip_perir_ctrl,
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+ .ctrlbit = (1 << 14),
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+ }, {
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+ .name = "usbhost",
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+ .id = -1,
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+ .enable = s5pv310_clk_ip_fsys_ctrl ,
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+ .ctrlbit = (1 << 12),
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+ }, {
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+ .name = "otg",
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+ .id = -1,
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+ .enable = s5pv310_clk_ip_fsys_ctrl,
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+ .ctrlbit = (1 << 13),
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+ }, {
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+ .name = "spi",
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+ .id = 0,
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+ .enable = s5pv310_clk_ip_peril_ctrl,
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+ .ctrlbit = (1 << 16),
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+ }, {
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+ .name = "spi",
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+ .id = 1,
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+ .enable = s5pv310_clk_ip_peril_ctrl,
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+ .ctrlbit = (1 << 17),
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+ }, {
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+ .name = "spi",
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+ .id = 2,
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+ .enable = s5pv310_clk_ip_peril_ctrl,
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+ .ctrlbit = (1 << 18),
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+ }, {
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+ .name = "fimg2d",
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+ .id = -1,
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+ .enable = s5pv310_clk_ip_image_ctrl,
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+ .ctrlbit = (1 << 0),
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+ }, {
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+ .name = "i2c",
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+ .id = 0,
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+ .parent = &clk_aclk_100.clk,
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+ .enable = s5pv310_clk_ip_peril_ctrl,
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+ .ctrlbit = (1 << 6),
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+ }, {
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+ .name = "i2c",
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+ .id = 1,
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+ .parent = &clk_aclk_100.clk,
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+ .enable = s5pv310_clk_ip_peril_ctrl,
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+ .ctrlbit = (1 << 7),
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+ }, {
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+ .name = "i2c",
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+ .id = 2,
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+ .parent = &clk_aclk_100.clk,
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+ .enable = s5pv310_clk_ip_peril_ctrl,
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+ .ctrlbit = (1 << 8),
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+ }, {
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+ .name = "i2c",
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+ .id = 3,
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+ .parent = &clk_aclk_100.clk,
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+ .enable = s5pv310_clk_ip_peril_ctrl,
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+ .ctrlbit = (1 << 9),
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+ }, {
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+ .name = "i2c",
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+ .id = 4,
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+ .parent = &clk_aclk_100.clk,
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+ .enable = s5pv310_clk_ip_peril_ctrl,
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+ .ctrlbit = (1 << 10),
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+ }, {
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+ .name = "i2c",
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+ .id = 5,
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+ .parent = &clk_aclk_100.clk,
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+ .enable = s5pv310_clk_ip_peril_ctrl,
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+ .ctrlbit = (1 << 11),
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+ }, {
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+ .name = "i2c",
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+ .id = 6,
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+ .parent = &clk_aclk_100.clk,
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+ .enable = s5pv310_clk_ip_peril_ctrl,
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+ .ctrlbit = (1 << 12),
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+ }, {
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+ .name = "i2c",
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+ .id = 7,
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+ .parent = &clk_aclk_100.clk,
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+ .enable = s5pv310_clk_ip_peril_ctrl,
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+ .ctrlbit = (1 << 13),
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+ },
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};
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static struct clk init_clocks[] = {
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@@ -387,6 +600,9 @@ static struct clk *clkset_group_list[] = {
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[0] = &clk_ext_xtal_mux,
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[1] = &clk_xusbxti,
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[2] = &clk_sclk_hdmi27m,
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+ [3] = &clk_sclk_usbphy0,
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+ [4] = &clk_sclk_usbphy1,
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+ [5] = &clk_sclk_hdmiphy,
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[6] = &clk_mout_mpll.clk,
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[7] = &clk_mout_epll.clk,
|
|
|
[8] = &clk_sclk_vpll.clk,
|
|
@@ -397,6 +613,104 @@ static struct clksrc_sources clkset_group = {
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|
|
.nr_sources = ARRAY_SIZE(clkset_group_list),
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|
|
};
|
|
|
|
|
|
+static struct clk *clkset_mout_g2d0_list[] = {
|
|
|
+ [0] = &clk_mout_mpll.clk,
|
|
|
+ [1] = &clk_sclk_apll.clk,
|
|
|
+};
|
|
|
+
|
|
|
+static struct clksrc_sources clkset_mout_g2d0 = {
|
|
|
+ .sources = clkset_mout_g2d0_list,
|
|
|
+ .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clksrc_clk clk_mout_g2d0 = {
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|
|
+ .clk = {
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|
|
+ .name = "mout_g2d0",
|
|
|
+ .id = -1,
|
|
|
+ },
|
|
|
+ .sources = &clkset_mout_g2d0,
|
|
|
+ .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk *clkset_mout_g2d1_list[] = {
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|
|
+ [0] = &clk_mout_epll.clk,
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|
|
+ [1] = &clk_sclk_vpll.clk,
|
|
|
+};
|
|
|
+
|
|
|
+static struct clksrc_sources clkset_mout_g2d1 = {
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|
|
+ .sources = clkset_mout_g2d1_list,
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|
+ .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
|
|
|
+};
|
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|
+
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|
|
+static struct clksrc_clk clk_mout_g2d1 = {
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|
|
+ .clk = {
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|
+ .name = "mout_g2d1",
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|
|
+ .id = -1,
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|
|
+ },
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|
+ .sources = &clkset_mout_g2d1,
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|
|
+ .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
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|
|
+};
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|
+
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|
|
+static struct clk *clkset_mout_g2d_list[] = {
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|
|
+ [0] = &clk_mout_g2d0.clk,
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|
|
+ [1] = &clk_mout_g2d1.clk,
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|
|
+};
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|
|
+
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|
|
+static struct clksrc_sources clkset_mout_g2d = {
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|
|
+ .sources = clkset_mout_g2d_list,
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|
|
+ .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
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|
|
+};
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|
+
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|
|
+static struct clksrc_clk clk_dout_mmc0 = {
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|
|
+ .clk = {
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|
+ .name = "dout_mmc0",
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|
+ .id = -1,
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|
|
+ },
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|
|
+ .sources = &clkset_group,
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|
|
+ .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
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|
|
+ .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
|
|
|
+};
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|
+
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|
|
+static struct clksrc_clk clk_dout_mmc1 = {
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|
|
+ .clk = {
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|
+ .name = "dout_mmc1",
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|
|
+ .id = -1,
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|
|
+ },
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|
|
+ .sources = &clkset_group,
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|
|
+ .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
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|
|
+ .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
|
|
|
+};
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|
|
+
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|
|
+static struct clksrc_clk clk_dout_mmc2 = {
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|
|
+ .clk = {
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|
|
+ .name = "dout_mmc2",
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|
|
+ .id = -1,
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|
|
+ },
|
|
|
+ .sources = &clkset_group,
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|
|
+ .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clksrc_clk clk_dout_mmc3 = {
|
|
|
+ .clk = {
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|
|
+ .name = "dout_mmc3",
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|
|
+ .id = -1,
|
|
|
+ },
|
|
|
+ .sources = &clkset_group,
|
|
|
+ .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clksrc_clk clk_dout_mmc4 = {
|
|
|
+ .clk = {
|
|
|
+ .name = "dout_mmc4",
|
|
|
+ .id = -1,
|
|
|
+ },
|
|
|
+ .sources = &clkset_group,
|
|
|
+ .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
|
|
|
+};
|
|
|
+
|
|
|
static struct clksrc_clk clksrcs[] = {
|
|
|
{
|
|
|
.clk = {
|
|
@@ -448,7 +762,200 @@ static struct clksrc_clk clksrcs[] = {
|
|
|
.sources = &clkset_group,
|
|
|
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
|
|
|
.reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
|
|
|
- },
|
|
|
+ }, {
|
|
|
+ .clk = {
|
|
|
+ .name = "sclk_csis",
|
|
|
+ .id = 0,
|
|
|
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
|
|
|
+ .ctrlbit = (1 << 24),
|
|
|
+ },
|
|
|
+ .sources = &clkset_group,
|
|
|
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
|
|
|
+ }, {
|
|
|
+ .clk = {
|
|
|
+ .name = "sclk_csis",
|
|
|
+ .id = 1,
|
|
|
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
|
|
|
+ .ctrlbit = (1 << 28),
|
|
|
+ },
|
|
|
+ .sources = &clkset_group,
|
|
|
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
|
|
|
+ }, {
|
|
|
+ .clk = {
|
|
|
+ .name = "sclk_cam",
|
|
|
+ .id = 0,
|
|
|
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
|
|
|
+ .ctrlbit = (1 << 16),
|
|
|
+ },
|
|
|
+ .sources = &clkset_group,
|
|
|
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
|
|
|
+ }, {
|
|
|
+ .clk = {
|
|
|
+ .name = "sclk_cam",
|
|
|
+ .id = 1,
|
|
|
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
|
|
|
+ .ctrlbit = (1 << 20),
|
|
|
+ },
|
|
|
+ .sources = &clkset_group,
|
|
|
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
|
|
|
+ }, {
|
|
|
+ .clk = {
|
|
|
+ .name = "sclk_fimc",
|
|
|
+ .id = 0,
|
|
|
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
|
|
|
+ .ctrlbit = (1 << 0),
|
|
|
+ },
|
|
|
+ .sources = &clkset_group,
|
|
|
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
|
|
|
+ }, {
|
|
|
+ .clk = {
|
|
|
+ .name = "sclk_fimc",
|
|
|
+ .id = 1,
|
|
|
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
|
|
|
+ .ctrlbit = (1 << 4),
|
|
|
+ },
|
|
|
+ .sources = &clkset_group,
|
|
|
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
|
|
|
+ }, {
|
|
|
+ .clk = {
|
|
|
+ .name = "sclk_fimc",
|
|
|
+ .id = 2,
|
|
|
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
|
|
|
+ .ctrlbit = (1 << 8),
|
|
|
+ },
|
|
|
+ .sources = &clkset_group,
|
|
|
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
|
|
|
+ }, {
|
|
|
+ .clk = {
|
|
|
+ .name = "sclk_fimc",
|
|
|
+ .id = 3,
|
|
|
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
|
|
|
+ .ctrlbit = (1 << 12),
|
|
|
+ },
|
|
|
+ .sources = &clkset_group,
|
|
|
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
|
|
|
+ }, {
|
|
|
+ .clk = {
|
|
|
+ .name = "sclk_fimd",
|
|
|
+ .id = 0,
|
|
|
+ .enable = s5pv310_clksrc_mask_lcd0_ctrl,
|
|
|
+ .ctrlbit = (1 << 0),
|
|
|
+ },
|
|
|
+ .sources = &clkset_group,
|
|
|
+ .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
|
|
|
+ }, {
|
|
|
+ .clk = {
|
|
|
+ .name = "sclk_fimd",
|
|
|
+ .id = 1,
|
|
|
+ .enable = s5pv310_clksrc_mask_lcd1_ctrl,
|
|
|
+ .ctrlbit = (1 << 0),
|
|
|
+ },
|
|
|
+ .sources = &clkset_group,
|
|
|
+ .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
|
|
|
+ }, {
|
|
|
+ .clk = {
|
|
|
+ .name = "sclk_sata",
|
|
|
+ .id = -1,
|
|
|
+ .enable = s5pv310_clksrc_mask_fsys_ctrl,
|
|
|
+ .ctrlbit = (1 << 24),
|
|
|
+ },
|
|
|
+ .sources = &clkset_mout_corebus,
|
|
|
+ .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
|
|
|
+ }, {
|
|
|
+ .clk = {
|
|
|
+ .name = "sclk_spi",
|
|
|
+ .id = 0,
|
|
|
+ .enable = s5pv310_clksrc_mask_peril1_ctrl,
|
|
|
+ .ctrlbit = (1 << 16),
|
|
|
+ },
|
|
|
+ .sources = &clkset_group,
|
|
|
+ .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
|
|
|
+ }, {
|
|
|
+ .clk = {
|
|
|
+ .name = "sclk_spi",
|
|
|
+ .id = 1,
|
|
|
+ .enable = s5pv310_clksrc_mask_peril1_ctrl,
|
|
|
+ .ctrlbit = (1 << 20),
|
|
|
+ },
|
|
|
+ .sources = &clkset_group,
|
|
|
+ .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
|
|
|
+ }, {
|
|
|
+ .clk = {
|
|
|
+ .name = "sclk_spi",
|
|
|
+ .id = 2,
|
|
|
+ .enable = s5pv310_clksrc_mask_peril1_ctrl,
|
|
|
+ .ctrlbit = (1 << 24),
|
|
|
+ },
|
|
|
+ .sources = &clkset_group,
|
|
|
+ .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
|
|
|
+ }, {
|
|
|
+ .clk = {
|
|
|
+ .name = "sclk_fimg2d",
|
|
|
+ .id = -1,
|
|
|
+ },
|
|
|
+ .sources = &clkset_mout_g2d,
|
|
|
+ .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
|
|
|
+ }, {
|
|
|
+ .clk = {
|
|
|
+ .name = "sclk_mmc",
|
|
|
+ .id = 0,
|
|
|
+ .parent = &clk_dout_mmc0.clk,
|
|
|
+ .enable = s5pv310_clksrc_mask_fsys_ctrl,
|
|
|
+ .ctrlbit = (1 << 0),
|
|
|
+ },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
|
|
|
+ }, {
|
|
|
+ .clk = {
|
|
|
+ .name = "sclk_mmc",
|
|
|
+ .id = 1,
|
|
|
+ .parent = &clk_dout_mmc1.clk,
|
|
|
+ .enable = s5pv310_clksrc_mask_fsys_ctrl,
|
|
|
+ .ctrlbit = (1 << 4),
|
|
|
+ },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
|
|
|
+ }, {
|
|
|
+ .clk = {
|
|
|
+ .name = "sclk_mmc",
|
|
|
+ .id = 2,
|
|
|
+ .parent = &clk_dout_mmc2.clk,
|
|
|
+ .enable = s5pv310_clksrc_mask_fsys_ctrl,
|
|
|
+ .ctrlbit = (1 << 8),
|
|
|
+ },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
|
|
|
+ }, {
|
|
|
+ .clk = {
|
|
|
+ .name = "sclk_mmc",
|
|
|
+ .id = 3,
|
|
|
+ .parent = &clk_dout_mmc3.clk,
|
|
|
+ .enable = s5pv310_clksrc_mask_fsys_ctrl,
|
|
|
+ .ctrlbit = (1 << 12),
|
|
|
+ },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
|
|
|
+ }, {
|
|
|
+ .clk = {
|
|
|
+ .name = "sclk_mmc",
|
|
|
+ .id = 4,
|
|
|
+ .parent = &clk_dout_mmc4.clk,
|
|
|
+ .enable = s5pv310_clksrc_mask_fsys_ctrl,
|
|
|
+ .ctrlbit = (1 << 16),
|
|
|
+ },
|
|
|
+ .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
|
|
|
+ }
|
|
|
};
|
|
|
|
|
|
/* Clock initialization code */
|
|
@@ -464,8 +971,6 @@ static struct clksrc_clk *sysclks[] = {
|
|
|
&clk_aclk_cores,
|
|
|
&clk_aclk_corem1,
|
|
|
&clk_periphclk,
|
|
|
- &clk_atclk,
|
|
|
- &clk_pclk_dbg,
|
|
|
&clk_mout_corebus,
|
|
|
&clk_sclk_dmc,
|
|
|
&clk_aclk_cored,
|
|
@@ -478,6 +983,11 @@ static struct clksrc_clk *sysclks[] = {
|
|
|
&clk_aclk_100,
|
|
|
&clk_aclk_160,
|
|
|
&clk_aclk_133,
|
|
|
+ &clk_dout_mmc0,
|
|
|
+ &clk_dout_mmc1,
|
|
|
+ &clk_dout_mmc2,
|
|
|
+ &clk_dout_mmc3,
|
|
|
+ &clk_dout_mmc4,
|
|
|
};
|
|
|
|
|
|
void __init_or_cpufreq s5pv310_setup_clocks(void)
|
|
@@ -490,15 +1000,11 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
|
|
|
unsigned long vpllsrc;
|
|
|
unsigned long xtal;
|
|
|
unsigned long armclk;
|
|
|
- unsigned long aclk_corem0;
|
|
|
- unsigned long aclk_cores;
|
|
|
- unsigned long aclk_corem1;
|
|
|
- unsigned long periphclk;
|
|
|
unsigned long sclk_dmc;
|
|
|
- unsigned long aclk_cored;
|
|
|
- unsigned long aclk_corep;
|
|
|
- unsigned long aclk_acp;
|
|
|
- unsigned long pclk_acp;
|
|
|
+ unsigned long aclk_200;
|
|
|
+ unsigned long aclk_100;
|
|
|
+ unsigned long aclk_160;
|
|
|
+ unsigned long aclk_133;
|
|
|
unsigned int ptr;
|
|
|
|
|
|
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
|
|
@@ -529,26 +1035,21 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
|
|
|
apll, mpll, epll, vpll);
|
|
|
|
|
|
armclk = clk_get_rate(&clk_armclk.clk);
|
|
|
- aclk_corem0 = clk_get_rate(&clk_aclk_corem0.clk);
|
|
|
- aclk_cores = clk_get_rate(&clk_aclk_cores.clk);
|
|
|
- aclk_corem1 = clk_get_rate(&clk_aclk_corem1.clk);
|
|
|
- periphclk = clk_get_rate(&clk_periphclk.clk);
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sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
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- aclk_cored = clk_get_rate(&clk_aclk_cored.clk);
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- aclk_corep = clk_get_rate(&clk_aclk_corep.clk);
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- aclk_acp = clk_get_rate(&clk_aclk_acp.clk);
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- pclk_acp = clk_get_rate(&clk_pclk_acp.clk);
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-
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- printk(KERN_INFO "S5PV310: ARMCLK=%ld, COREM0=%ld, CORES=%ld\n"
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- "COREM1=%ld, PERI=%ld, DMC=%ld, CORED=%ld\n"
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- "COREP=%ld, ACLK_ACP=%ld, PCLK_ACP=%ld",
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- armclk, aclk_corem0, aclk_cores, aclk_corem1,
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- periphclk, sclk_dmc, aclk_cored, aclk_corep,
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- aclk_acp, pclk_acp);
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+
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+ aclk_200 = clk_get_rate(&clk_aclk_200.clk);
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+ aclk_100 = clk_get_rate(&clk_aclk_100.clk);
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+ aclk_160 = clk_get_rate(&clk_aclk_160.clk);
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+ aclk_133 = clk_get_rate(&clk_aclk_133.clk);
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|
+
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+ printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
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+ "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
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+ armclk, sclk_dmc, aclk_200,
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+ aclk_100, aclk_160, aclk_133);
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|
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clk_f.rate = armclk;
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clk_h.rate = sclk_dmc;
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- clk_p.rate = periphclk;
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+ clk_p.rate = aclk_100;
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|
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for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
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s3c_set_clksrc(&clksrcs[ptr], true);
|