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@@ -1145,6 +1145,7 @@ static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
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static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
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{
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u32 fuse;
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+ s8 rom = 0, metal = 0, pg_ver = 0, rdl_ver = 0;
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int ret;
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ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
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@@ -1155,8 +1156,29 @@ static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
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if (ret < 0)
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goto out;
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+ pg_ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET;
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+ rom = (fuse & WL18XX_ROM_VER_MASK) >> WL18XX_ROM_VER_OFFSET;
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+
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+ if (rom <= 0xE)
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+ metal = (fuse & WL18XX_METAL_VER_MASK) >>
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+ WL18XX_METAL_VER_OFFSET;
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+ else
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+ metal = (fuse & WL18XX_NEW_METAL_VER_MASK) >>
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+ WL18XX_NEW_METAL_VER_OFFSET;
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+
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+ ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_2_3, &fuse);
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+ if (ret < 0)
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+ goto out;
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+
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+ rdl_ver = (fuse & WL18XX_RDL_VER_MASK) >> WL18XX_RDL_VER_OFFSET;
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+ if (rdl_ver > RDL_MAX)
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+ rdl_ver = RDL_NONE;
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+
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+ wl1271_info("wl18xx HW: RDL %d, %s, PG %x.%x (ROM %x)",
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+ rdl_ver, rdl_names[rdl_ver], pg_ver, metal, rom);
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+
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if (ver)
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- *ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET;
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+ *ver = pg_ver;
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ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
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