|
@@ -59,6 +59,12 @@ static struct pci_device_id megasas_pci_table[] = {
|
|
PCI_ANY_ID,
|
|
PCI_ANY_ID,
|
|
PCI_ANY_ID,
|
|
PCI_ANY_ID,
|
|
},
|
|
},
|
|
|
|
+ {
|
|
|
|
+ PCI_VENDOR_ID_LSI_LOGIC,
|
|
|
|
+ PCI_DEVICE_ID_LSI_SAS1078R, // ppc IOP
|
|
|
|
+ PCI_ANY_ID,
|
|
|
|
+ PCI_ANY_ID,
|
|
|
|
+ },
|
|
{
|
|
{
|
|
PCI_VENDOR_ID_DELL,
|
|
PCI_VENDOR_ID_DELL,
|
|
PCI_DEVICE_ID_DELL_PERC5, // xscale IOP
|
|
PCI_DEVICE_ID_DELL_PERC5, // xscale IOP
|
|
@@ -198,6 +204,86 @@ static struct megasas_instance_template megasas_instance_template_xscale = {
|
|
* to xscale (deviceid : 1064R, PERC5) controllers
|
|
* to xscale (deviceid : 1064R, PERC5) controllers
|
|
*/
|
|
*/
|
|
|
|
|
|
|
|
+/**
|
|
|
|
+* The following functions are defined for ppc (deviceid : 0x60)
|
|
|
|
+* controllers
|
|
|
|
+*/
|
|
|
|
+
|
|
|
|
+/**
|
|
|
|
+ * megasas_enable_intr_ppc - Enables interrupts
|
|
|
|
+ * @regs: MFI register set
|
|
|
|
+ */
|
|
|
|
+static inline void
|
|
|
|
+megasas_enable_intr_ppc(struct megasas_register_set __iomem * regs)
|
|
|
|
+{
|
|
|
|
+ writel(0xFFFFFFFF, &(regs)->outbound_doorbell_clear);
|
|
|
|
+
|
|
|
|
+ writel(~0x80000004, &(regs)->outbound_intr_mask);
|
|
|
|
+
|
|
|
|
+ /* Dummy readl to force pci flush */
|
|
|
|
+ readl(®s->outbound_intr_mask);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+/**
|
|
|
|
+ * megasas_read_fw_status_reg_ppc - returns the current FW status value
|
|
|
|
+ * @regs: MFI register set
|
|
|
|
+ */
|
|
|
|
+static u32
|
|
|
|
+megasas_read_fw_status_reg_ppc(struct megasas_register_set __iomem * regs)
|
|
|
|
+{
|
|
|
|
+ return readl(&(regs)->outbound_scratch_pad);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+/**
|
|
|
|
+ * megasas_clear_interrupt_ppc - Check & clear interrupt
|
|
|
|
+ * @regs: MFI register set
|
|
|
|
+ */
|
|
|
|
+static int
|
|
|
|
+megasas_clear_intr_ppc(struct megasas_register_set __iomem * regs)
|
|
|
|
+{
|
|
|
|
+ u32 status;
|
|
|
|
+ /*
|
|
|
|
+ * Check if it is our interrupt
|
|
|
|
+ */
|
|
|
|
+ status = readl(®s->outbound_intr_status);
|
|
|
|
+
|
|
|
|
+ if (!(status & MFI_REPLY_1078_MESSAGE_INTERRUPT)) {
|
|
|
|
+ return 1;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ /*
|
|
|
|
+ * Clear the interrupt by writing back the same value
|
|
|
|
+ */
|
|
|
|
+ writel(status, ®s->outbound_doorbell_clear);
|
|
|
|
+
|
|
|
|
+ return 0;
|
|
|
|
+}
|
|
|
|
+/**
|
|
|
|
+ * megasas_fire_cmd_ppc - Sends command to the FW
|
|
|
|
+ * @frame_phys_addr : Physical address of cmd
|
|
|
|
+ * @frame_count : Number of frames for the command
|
|
|
|
+ * @regs : MFI register set
|
|
|
|
+ */
|
|
|
|
+static inline void
|
|
|
|
+megasas_fire_cmd_ppc(dma_addr_t frame_phys_addr, u32 frame_count, struct megasas_register_set __iomem *regs)
|
|
|
|
+{
|
|
|
|
+ writel((frame_phys_addr | (frame_count<<1))|1,
|
|
|
|
+ &(regs)->inbound_queue_port);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static struct megasas_instance_template megasas_instance_template_ppc = {
|
|
|
|
+
|
|
|
|
+ .fire_cmd = megasas_fire_cmd_ppc,
|
|
|
|
+ .enable_intr = megasas_enable_intr_ppc,
|
|
|
|
+ .clear_intr = megasas_clear_intr_ppc,
|
|
|
|
+ .read_fw_status_reg = megasas_read_fw_status_reg_ppc,
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+/**
|
|
|
|
+* This is the end of set of functions & definitions
|
|
|
|
+* specific to ppc (deviceid : 0x60) controllers
|
|
|
|
+*/
|
|
|
|
+
|
|
/**
|
|
/**
|
|
* megasas_disable_intr - Disables interrupts
|
|
* megasas_disable_intr - Disables interrupts
|
|
* @regs: MFI register set
|
|
* @regs: MFI register set
|
|
@@ -1607,7 +1693,17 @@ static int megasas_init_mfi(struct megasas_instance *instance)
|
|
|
|
|
|
reg_set = instance->reg_set;
|
|
reg_set = instance->reg_set;
|
|
|
|
|
|
- instance->instancet = &megasas_instance_template_xscale;
|
|
|
|
|
|
+ switch(instance->pdev->device)
|
|
|
|
+ {
|
|
|
|
+ case PCI_DEVICE_ID_LSI_SAS1078R:
|
|
|
|
+ instance->instancet = &megasas_instance_template_ppc;
|
|
|
|
+ break;
|
|
|
|
+ case PCI_DEVICE_ID_LSI_SAS1064R:
|
|
|
|
+ case PCI_DEVICE_ID_DELL_PERC5:
|
|
|
|
+ default:
|
|
|
|
+ instance->instancet = &megasas_instance_template_xscale;
|
|
|
|
+ break;
|
|
|
|
+ }
|
|
|
|
|
|
/*
|
|
/*
|
|
* We expect the FW state to be READY
|
|
* We expect the FW state to be READY
|