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@@ -118,22 +118,25 @@ static void radeon_show_cursor(struct drm_crtc *crtc)
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}
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static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
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- uint32_t gpu_addr)
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+ uint64_t gpu_addr)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct radeon_device *rdev = crtc->dev->dev_private;
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if (ASIC_IS_DCE4(rdev)) {
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- WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 0);
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- WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr);
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+ WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
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+ upper_32_bits(gpu_addr));
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+ WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
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+ gpu_addr & 0xffffffff);
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} else if (ASIC_IS_AVIVO(rdev)) {
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if (rdev->family >= CHIP_RV770) {
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if (radeon_crtc->crtc_id)
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- WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, 0);
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+ WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
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else
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- WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, 0);
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+ WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
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}
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- WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr);
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+ WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
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+ gpu_addr & 0xffffffff);
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} else {
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radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr;
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/* offset is from DISP(2)_BASE_ADDRESS */
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