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@@ -35,9 +35,15 @@
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#define MCFINT_VECBASE 64 /* Vector base number */
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#define MCFINT_UART0 13 /* Interrupt number for UART0 */
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+#define MCFINT_UART1 14 /* Interrupt number for UART1 */
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+#define MCFINT_UART2 15 /* Interrupt number for UART2 */
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#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
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#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
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+#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
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+#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
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+#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
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+
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/*
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* SDRAM configuration registers.
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*/
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@@ -58,9 +64,9 @@
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/*
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* UART module.
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*/
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-#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000200)
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-#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000240)
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-#define MCFUART_BASE3 (MCF_IPSBAR + 0x00000280)
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+#define MCFUART_BASE0 (MCF_IPSBAR + 0x00000200)
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+#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000240)
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+#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000280)
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/*
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* FEC ethernet module.
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