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@@ -445,8 +445,8 @@ int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
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void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
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{
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- efx_oword_t tx_desc_ptr;
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struct efx_nic *efx = tx_queue->efx;
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+ efx_oword_t reg;
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tx_queue->flushed = FLUSH_NONE;
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@@ -454,7 +454,7 @@ void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
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efx_init_special_buffer(efx, &tx_queue->txd);
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/* Push TX descriptor ring to card */
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- EFX_POPULATE_OWORD_10(tx_desc_ptr,
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+ EFX_POPULATE_OWORD_10(reg,
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FRF_AZ_TX_DESCQ_EN, 1,
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FRF_AZ_TX_ISCSI_DDIG_EN, 0,
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FRF_AZ_TX_ISCSI_HDIG_EN, 0,
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@@ -470,17 +470,15 @@ void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
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if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
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int csum = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
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- EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
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- EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS,
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+ EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
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+ EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_TCP_CHKSM_DIS,
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!csum);
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}
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- efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
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+ efx_writeo_table(efx, ®, efx->type->txd_ptr_tbl_base,
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tx_queue->queue);
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if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
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- efx_oword_t reg;
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-
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/* Only 128 bits in this register */
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BUILD_BUG_ON(EFX_MAX_TX_QUEUES > 128);
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@@ -491,6 +489,16 @@ void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
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set_bit_le(tx_queue->queue, (void *)®);
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efx_writeo(efx, ®, FR_AA_TX_CHKSM_CFG);
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}
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+
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+ if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
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+ EFX_POPULATE_OWORD_1(reg,
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+ FRF_BZ_TX_PACE,
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+ (tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ?
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+ FFE_BZ_TX_PACE_OFF :
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+ FFE_BZ_TX_PACE_RESERVED);
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+ efx_writeo_table(efx, ®, FR_BZ_TX_PACE_TBL,
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+ tx_queue->queue);
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+ }
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}
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static void efx_flush_tx_queue(struct efx_tx_queue *tx_queue)
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@@ -1238,8 +1246,10 @@ int efx_nic_flush_queues(struct efx_nic *efx)
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/* Flush all tx queues in parallel */
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efx_for_each_channel(channel, efx) {
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- efx_for_each_channel_tx_queue(tx_queue, channel)
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- efx_flush_tx_queue(tx_queue);
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+ efx_for_each_possible_channel_tx_queue(tx_queue, channel) {
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+ if (tx_queue->initialised)
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+ efx_flush_tx_queue(tx_queue);
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+ }
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}
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/* The hardware supports four concurrent rx flushes, each of which may
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@@ -1262,8 +1272,9 @@ int efx_nic_flush_queues(struct efx_nic *efx)
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++rx_pending;
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}
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}
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- efx_for_each_channel_tx_queue(tx_queue, channel) {
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- if (tx_queue->flushed != FLUSH_DONE)
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+ efx_for_each_possible_channel_tx_queue(tx_queue, channel) {
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+ if (tx_queue->initialised &&
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+ tx_queue->flushed != FLUSH_DONE)
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++tx_pending;
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}
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}
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@@ -1278,8 +1289,9 @@ int efx_nic_flush_queues(struct efx_nic *efx)
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/* Mark the queues as all flushed. We're going to return failure
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* leading to a reset, or fake up success anyway */
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efx_for_each_channel(channel, efx) {
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- efx_for_each_channel_tx_queue(tx_queue, channel) {
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- if (tx_queue->flushed != FLUSH_DONE)
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+ efx_for_each_possible_channel_tx_queue(tx_queue, channel) {
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+ if (tx_queue->initialised &&
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+ tx_queue->flushed != FLUSH_DONE)
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netif_err(efx, hw, efx->net_dev,
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"tx queue %d flush command timed out\n",
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tx_queue->queue);
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@@ -1682,6 +1694,19 @@ void efx_nic_init_common(struct efx_nic *efx)
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if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
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EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
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efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
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+
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+ if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
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+ EFX_POPULATE_OWORD_4(temp,
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+ /* Default values */
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+ FRF_BZ_TX_PACE_SB_NOT_AF, 0x15,
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+ FRF_BZ_TX_PACE_SB_AF, 0xb,
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+ FRF_BZ_TX_PACE_FB_BASE, 0,
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+ /* Allow large pace values in the
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+ * fast bin. */
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+ FRF_BZ_TX_PACE_BIN_TH,
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+ FFE_BZ_TX_PACE_RESERVED);
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+ efx_writeo(efx, &temp, FR_BZ_TX_PACE);
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+ }
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}
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/* Register dump */
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