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@@ -189,6 +189,21 @@ static int mmci_validate_data(struct mmci_host *host,
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return 0;
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}
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+static void mmci_reg_delay(struct mmci_host *host)
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+{
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+ /*
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+ * According to the spec, at least three feedback clock cycles
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+ * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
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+ * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
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+ * Worst delay time during card init is at 100 kHz => 30 us.
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+ * Worst delay time when up and running is at 25 MHz => 120 ns.
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+ */
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+ if (host->cclk < 25000000)
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+ udelay(30);
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+ else
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+ ndelay(120);
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+}
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+
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/*
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* This must be called with host->lock held
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*/
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@@ -1264,6 +1279,7 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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mmci_set_clkreg(host, ios->clock);
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mmci_write_pwrreg(host, pwr);
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+ mmci_reg_delay(host);
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spin_unlock_irqrestore(&host->lock, flags);
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