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+/*
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+ * charon board Device Tree Source
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+ *
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+ * Copyright (C) 2007 Semihalf
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+ * Marian Balakowicz <m8@semihalf.com>
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+ *
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+ * Copyright (C) 2010 DENX Software Engineering GmbH
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+ * Heiko Schocher <hs@denx.de>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ */
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+
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+/dts-v1/;
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+
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+/ {
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+ model = "anon,charon";
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+ compatible = "anon,charon";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ interrupt-parent = <&mpc5200_pic>;
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+
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ PowerPC,5200@0 {
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+ device_type = "cpu";
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+ reg = <0>;
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+ d-cache-line-size = <32>;
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+ i-cache-line-size = <32>;
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+ d-cache-size = <0x4000>; // L1, 16K
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+ i-cache-size = <0x4000>; // L1, 16K
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+ timebase-frequency = <0>; // from bootloader
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+ bus-frequency = <0>; // from bootloader
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+ clock-frequency = <0>; // from bootloader
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+ };
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+ };
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+
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+ memory {
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+ device_type = "memory";
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+ reg = <0x00000000 0x08000000>; // 128MB
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+ };
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+
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+ soc5200@f0000000 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "fsl,mpc5200-immr";
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+ ranges = <0 0xf0000000 0x0000c000>;
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+ reg = <0xf0000000 0x00000100>;
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+ bus-frequency = <0>; // from bootloader
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+ system-frequency = <0>; // from bootloader
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+
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+ cdm@200 {
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+ compatible = "fsl,mpc5200-cdm";
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+ reg = <0x200 0x38>;
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+ };
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+
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+ mpc5200_pic: interrupt-controller@500 {
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+ // 5200 interrupts are encoded into two levels;
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+ interrupt-controller;
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+ #interrupt-cells = <3>;
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+ compatible = "fsl,mpc5200-pic";
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+ reg = <0x500 0x80>;
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+ };
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+
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+ timer@600 { // General Purpose Timer
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+ compatible = "fsl,mpc5200-gpt";
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+ reg = <0x600 0x10>;
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+ interrupts = <1 9 0>;
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+ fsl,has-wdt;
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+ };
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+
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+ can@900 {
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+ compatible = "fsl,mpc5200-mscan";
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+ interrupts = <2 17 0>;
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+ reg = <0x900 0x80>;
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+ };
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+
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+ can@980 {
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+ compatible = "fsl,mpc5200-mscan";
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+ interrupts = <2 18 0>;
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+ reg = <0x980 0x80>;
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+ };
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+
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+ gpio_simple: gpio@b00 {
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+ compatible = "fsl,mpc5200-gpio";
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+ reg = <0xb00 0x40>;
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+ interrupts = <1 7 0>;
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ };
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+
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+ usb@1000 {
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+ compatible = "fsl,mpc5200-ohci","ohci-be";
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+ reg = <0x1000 0xff>;
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+ interrupts = <2 6 0>;
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+ };
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+
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+ dma-controller@1200 {
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+ device_type = "dma-controller";
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+ compatible = "fsl,mpc5200-bestcomm";
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+ reg = <0x1200 0x80>;
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+ interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
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+ 3 4 0 3 5 0 3 6 0 3 7 0
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+ 3 8 0 3 9 0 3 10 0 3 11 0
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+ 3 12 0 3 13 0 3 14 0 3 15 0>;
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+ };
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+
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+ xlb@1f00 {
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+ compatible = "fsl,mpc5200-xlb";
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+ reg = <0x1f00 0x100>;
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+ };
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+
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+ serial@2000 { // PSC1
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+ compatible = "fsl,mpc5200-psc-uart";
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+ reg = <0x2000 0x100>;
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+ interrupts = <2 1 0>;
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+ };
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+
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+ serial@2400 { // PSC3
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+ compatible = "fsl,mpc5200-psc-uart";
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+ reg = <0x2400 0x100>;
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+ interrupts = <2 3 0>;
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+ };
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+
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+ ethernet@3000 {
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+ compatible = "fsl,mpc5200-fec";
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+ reg = <0x3000 0x400>;
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+ local-mac-address = [ 00 00 00 00 00 00 ];
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+ interrupts = <2 5 0>;
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+ fixed-link = <1 1 100 0 0>;
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+ };
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+
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+ mdio@3000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "fsl,mpc5200-mdio";
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+ reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
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+ interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
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+ };
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+
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+ ata@3a00 {
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+ compatible = "fsl,mpc5200-ata";
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+ reg = <0x3a00 0x100>;
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+ interrupts = <2 7 0>;
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+ };
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+
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+ i2c@3d00 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "fsl,mpc5200-i2c","fsl-i2c";
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+ reg = <0x3d00 0x40>;
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+ interrupts = <2 15 0>;
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+ };
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+
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+
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+ i2c@3d40 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "fsl,mpc5200-i2c","fsl-i2c";
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+ reg = <0x3d40 0x40>;
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+ interrupts = <2 16 0>;
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+
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+ dtt@28 {
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+ compatible = "national,lm80";
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+ reg = <0x28>;
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+ };
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+
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+ rtc@68 {
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+ compatible = "dallas,ds1374";
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+ reg = <0x68>;
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+ };
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+ };
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+
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+ sram@8000 {
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+ compatible = "fsl,mpc5200-sram";
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+ reg = <0x8000 0x4000>;
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+ };
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+ };
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+
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+ localbus {
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+ compatible = "fsl,mpc5200-lpb","simple-bus";
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+ #address-cells = <2>;
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+ #size-cells = <1>;
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+ ranges = < 0 0 0xfc000000 0x02000000
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+ 1 0 0xe0000000 0x04000000 // CS1 range, SM501
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+ 3 0 0xe8000000 0x00080000>;
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+
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+ flash@0,0 {
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+ compatible = "cfi-flash";
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+ reg = <0 0 0x02000000>;
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+ bank-width = <4>;
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+ device-width = <2>;
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+ #size-cells = <1>;
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+ #address-cells = <1>;
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+ };
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+
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+ display@1,0 {
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+ compatible = "smi,sm501";
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+ reg = <1 0x00000000 0x00800000
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+ 1 0x03e00000 0x00200000>;
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+ mode = "640x480-32@60";
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+ interrupts = <1 1 3>;
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+ little-endian;
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+ };
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+
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+ mram0@3,0 {
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+ compatible = "mtd-ram";
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+ reg = <3 0x00000 0x80000>;
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+ bank-width = <1>;
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+ };
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+ };
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+
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+ pci@f0000d00 {
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+ #interrupt-cells = <1>;
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+ #size-cells = <2>;
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+ #address-cells = <3>;
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+ device_type = "pci";
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+ compatible = "fsl,mpc5200-pci";
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+ reg = <0xf0000d00 0x100>;
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+ interrupt-map-mask = <0xf800 0 0 7>;
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+ interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
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+ 0xc000 0 0 2 &mpc5200_pic 0 0 3
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+ 0xc000 0 0 3 &mpc5200_pic 0 0 3
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+ 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
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+ clock-frequency = <0>; // From boot loader
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+ interrupts = <2 8 0 2 9 0 2 10 0>;
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+ bus-range = <0 0>;
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+ ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
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+ 0x02000000 0 0x90000000 0x90000000 0 0x10000000
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+ 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
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+ };
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+};
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Benjamin Herrenschmidt