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@@ -304,17 +304,25 @@ void __init arch_init_irq(void)
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case MIPS_REVISION_SCON_SOCIT:
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case MIPS_REVISION_SCON_ROCIT:
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if (cpu_has_veic)
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- init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
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+ init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
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+ MSC01E_INT_BASE, msc_eicirqmap,
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+ msc_nr_eicirqs);
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else
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- init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
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+ init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
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+ MSC01C_INT_BASE, msc_irqmap,
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+ msc_nr_irqs);
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break;
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case MIPS_REVISION_SCON_SOCITSC:
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case MIPS_REVISION_SCON_SOCITSCP:
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if (cpu_has_veic)
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- init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
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+ init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
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+ MSC01E_INT_BASE, msc_eicirqmap,
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+ msc_nr_eicirqs);
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else
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- init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
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+ init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
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+ MSC01C_INT_BASE, msc_irqmap,
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+ msc_nr_irqs);
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}
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if (cpu_has_veic) {
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@@ -345,11 +353,13 @@ void __init arch_init_irq(void)
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}
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#else /* Not SMTC */
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setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
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- setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
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+ setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
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+ &corehi_irqaction);
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#endif /* CONFIG_MIPS_MT_SMTC */
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}
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else {
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setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
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- setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
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+ setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
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+ &corehi_irqaction);
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}
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}
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