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@@ -0,0 +1,441 @@
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+#define VCPU_USR_REG(_reg_nr) (VCPU_USR_REGS + (_reg_nr * 4))
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+#define VCPU_USR_SP (VCPU_USR_REG(13))
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+#define VCPU_USR_LR (VCPU_USR_REG(14))
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+#define CP15_OFFSET(_cp15_reg_idx) (VCPU_CP15 + (_cp15_reg_idx * 4))
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+
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+/*
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+ * Many of these macros need to access the VCPU structure, which is always
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+ * held in r0. These macros should never clobber r1, as it is used to hold the
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+ * exception code on the return path (except of course the macro that switches
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+ * all the registers before the final jump to the VM).
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+ */
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+vcpu .req r0 @ vcpu pointer always in r0
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+
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+/* Clobbers {r2-r6} */
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+.macro store_vfp_state vfp_base
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+ @ The VFPFMRX and VFPFMXR macros are the VMRS and VMSR instructions
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+ VFPFMRX r2, FPEXC
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+ @ Make sure VFP is enabled so we can touch the registers.
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+ orr r6, r2, #FPEXC_EN
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+ VFPFMXR FPEXC, r6
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+
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+ VFPFMRX r3, FPSCR
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+ tst r2, #FPEXC_EX @ Check for VFP Subarchitecture
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+ beq 1f
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+ @ If FPEXC_EX is 0, then FPINST/FPINST2 reads are upredictable, so
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+ @ we only need to save them if FPEXC_EX is set.
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+ VFPFMRX r4, FPINST
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+ tst r2, #FPEXC_FP2V
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+ VFPFMRX r5, FPINST2, ne @ vmrsne
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+ bic r6, r2, #FPEXC_EX @ FPEXC_EX disable
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+ VFPFMXR FPEXC, r6
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+1:
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+ VFPFSTMIA \vfp_base, r6 @ Save VFP registers
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+ stm \vfp_base, {r2-r5} @ Save FPEXC, FPSCR, FPINST, FPINST2
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+.endm
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+
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+/* Assume FPEXC_EN is on and FPEXC_EX is off, clobbers {r2-r6} */
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+.macro restore_vfp_state vfp_base
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+ VFPFLDMIA \vfp_base, r6 @ Load VFP registers
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+ ldm \vfp_base, {r2-r5} @ Load FPEXC, FPSCR, FPINST, FPINST2
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+
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+ VFPFMXR FPSCR, r3
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+ tst r2, #FPEXC_EX @ Check for VFP Subarchitecture
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+ beq 1f
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+ VFPFMXR FPINST, r4
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+ tst r2, #FPEXC_FP2V
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+ VFPFMXR FPINST2, r5, ne
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+1:
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+ VFPFMXR FPEXC, r2 @ FPEXC (last, in case !EN)
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+.endm
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+
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+/* These are simply for the macros to work - value don't have meaning */
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+.equ usr, 0
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+.equ svc, 1
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+.equ abt, 2
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+.equ und, 3
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+.equ irq, 4
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+.equ fiq, 5
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+
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+.macro push_host_regs_mode mode
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+ mrs r2, SP_\mode
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+ mrs r3, LR_\mode
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+ mrs r4, SPSR_\mode
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+ push {r2, r3, r4}
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+.endm
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+
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+/*
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+ * Store all host persistent registers on the stack.
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+ * Clobbers all registers, in all modes, except r0 and r1.
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+ */
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+.macro save_host_regs
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+ /* Hyp regs. Only ELR_hyp (SPSR_hyp already saved) */
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+ mrs r2, ELR_hyp
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+ push {r2}
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+
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+ /* usr regs */
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+ push {r4-r12} @ r0-r3 are always clobbered
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+ mrs r2, SP_usr
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+ mov r3, lr
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+ push {r2, r3}
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+
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+ push_host_regs_mode svc
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+ push_host_regs_mode abt
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+ push_host_regs_mode und
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+ push_host_regs_mode irq
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+
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+ /* fiq regs */
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+ mrs r2, r8_fiq
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+ mrs r3, r9_fiq
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+ mrs r4, r10_fiq
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+ mrs r5, r11_fiq
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+ mrs r6, r12_fiq
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+ mrs r7, SP_fiq
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+ mrs r8, LR_fiq
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+ mrs r9, SPSR_fiq
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+ push {r2-r9}
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+.endm
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+
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+.macro pop_host_regs_mode mode
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+ pop {r2, r3, r4}
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+ msr SP_\mode, r2
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+ msr LR_\mode, r3
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+ msr SPSR_\mode, r4
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+.endm
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+
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+/*
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+ * Restore all host registers from the stack.
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+ * Clobbers all registers, in all modes, except r0 and r1.
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+ */
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+.macro restore_host_regs
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+ pop {r2-r9}
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+ msr r8_fiq, r2
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+ msr r9_fiq, r3
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+ msr r10_fiq, r4
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+ msr r11_fiq, r5
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+ msr r12_fiq, r6
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+ msr SP_fiq, r7
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+ msr LR_fiq, r8
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+ msr SPSR_fiq, r9
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+
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+ pop_host_regs_mode irq
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+ pop_host_regs_mode und
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+ pop_host_regs_mode abt
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+ pop_host_regs_mode svc
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+
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+ pop {r2, r3}
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+ msr SP_usr, r2
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+ mov lr, r3
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+ pop {r4-r12}
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+
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+ pop {r2}
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+ msr ELR_hyp, r2
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+.endm
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+
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+/*
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+ * Restore SP, LR and SPSR for a given mode. offset is the offset of
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+ * this mode's registers from the VCPU base.
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+ *
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+ * Assumes vcpu pointer in vcpu reg
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+ *
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+ * Clobbers r1, r2, r3, r4.
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+ */
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+.macro restore_guest_regs_mode mode, offset
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+ add r1, vcpu, \offset
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+ ldm r1, {r2, r3, r4}
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+ msr SP_\mode, r2
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+ msr LR_\mode, r3
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+ msr SPSR_\mode, r4
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+.endm
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+
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+/*
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+ * Restore all guest registers from the vcpu struct.
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+ *
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+ * Assumes vcpu pointer in vcpu reg
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+ *
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+ * Clobbers *all* registers.
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+ */
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+.macro restore_guest_regs
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+ restore_guest_regs_mode svc, #VCPU_SVC_REGS
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+ restore_guest_regs_mode abt, #VCPU_ABT_REGS
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+ restore_guest_regs_mode und, #VCPU_UND_REGS
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+ restore_guest_regs_mode irq, #VCPU_IRQ_REGS
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+
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+ add r1, vcpu, #VCPU_FIQ_REGS
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+ ldm r1, {r2-r9}
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+ msr r8_fiq, r2
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+ msr r9_fiq, r3
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+ msr r10_fiq, r4
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+ msr r11_fiq, r5
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+ msr r12_fiq, r6
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+ msr SP_fiq, r7
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+ msr LR_fiq, r8
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+ msr SPSR_fiq, r9
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+
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+ @ Load return state
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+ ldr r2, [vcpu, #VCPU_PC]
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+ ldr r3, [vcpu, #VCPU_CPSR]
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+ msr ELR_hyp, r2
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+ msr SPSR_cxsf, r3
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+
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+ @ Load user registers
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+ ldr r2, [vcpu, #VCPU_USR_SP]
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+ ldr r3, [vcpu, #VCPU_USR_LR]
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+ msr SP_usr, r2
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+ mov lr, r3
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+ add vcpu, vcpu, #(VCPU_USR_REGS)
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+ ldm vcpu, {r0-r12}
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+.endm
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+
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+/*
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+ * Save SP, LR and SPSR for a given mode. offset is the offset of
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+ * this mode's registers from the VCPU base.
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+ *
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+ * Assumes vcpu pointer in vcpu reg
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+ *
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+ * Clobbers r2, r3, r4, r5.
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+ */
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+.macro save_guest_regs_mode mode, offset
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+ add r2, vcpu, \offset
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+ mrs r3, SP_\mode
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+ mrs r4, LR_\mode
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+ mrs r5, SPSR_\mode
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+ stm r2, {r3, r4, r5}
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+.endm
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+
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+/*
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+ * Save all guest registers to the vcpu struct
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+ * Expects guest's r0, r1, r2 on the stack.
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+ *
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+ * Assumes vcpu pointer in vcpu reg
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+ *
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+ * Clobbers r2, r3, r4, r5.
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+ */
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+.macro save_guest_regs
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+ @ Store usr registers
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+ add r2, vcpu, #VCPU_USR_REG(3)
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+ stm r2, {r3-r12}
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+ add r2, vcpu, #VCPU_USR_REG(0)
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+ pop {r3, r4, r5} @ r0, r1, r2
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+ stm r2, {r3, r4, r5}
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+ mrs r2, SP_usr
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+ mov r3, lr
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+ str r2, [vcpu, #VCPU_USR_SP]
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+ str r3, [vcpu, #VCPU_USR_LR]
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+
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+ @ Store return state
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+ mrs r2, ELR_hyp
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+ mrs r3, spsr
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+ str r2, [vcpu, #VCPU_PC]
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+ str r3, [vcpu, #VCPU_CPSR]
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+
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+ @ Store other guest registers
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+ save_guest_regs_mode svc, #VCPU_SVC_REGS
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+ save_guest_regs_mode abt, #VCPU_ABT_REGS
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+ save_guest_regs_mode und, #VCPU_UND_REGS
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+ save_guest_regs_mode irq, #VCPU_IRQ_REGS
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+.endm
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+
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+/* Reads cp15 registers from hardware and stores them in memory
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+ * @store_to_vcpu: If 0, registers are written in-order to the stack,
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+ * otherwise to the VCPU struct pointed to by vcpup
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+ *
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+ * Assumes vcpu pointer in vcpu reg
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+ *
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+ * Clobbers r2 - r12
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+ */
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+.macro read_cp15_state store_to_vcpu
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+ mrc p15, 0, r2, c1, c0, 0 @ SCTLR
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+ mrc p15, 0, r3, c1, c0, 2 @ CPACR
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+ mrc p15, 0, r4, c2, c0, 2 @ TTBCR
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+ mrc p15, 0, r5, c3, c0, 0 @ DACR
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+ mrrc p15, 0, r6, r7, c2 @ TTBR 0
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+ mrrc p15, 1, r8, r9, c2 @ TTBR 1
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+ mrc p15, 0, r10, c10, c2, 0 @ PRRR
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+ mrc p15, 0, r11, c10, c2, 1 @ NMRR
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+ mrc p15, 2, r12, c0, c0, 0 @ CSSELR
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+
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+ .if \store_to_vcpu == 0
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+ push {r2-r12} @ Push CP15 registers
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+ .else
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+ str r2, [vcpu, #CP15_OFFSET(c1_SCTLR)]
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+ str r3, [vcpu, #CP15_OFFSET(c1_CPACR)]
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+ str r4, [vcpu, #CP15_OFFSET(c2_TTBCR)]
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+ str r5, [vcpu, #CP15_OFFSET(c3_DACR)]
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+ add r2, vcpu, #CP15_OFFSET(c2_TTBR0)
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+ strd r6, r7, [r2]
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+ add r2, vcpu, #CP15_OFFSET(c2_TTBR1)
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+ strd r8, r9, [r2]
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+ str r10, [vcpu, #CP15_OFFSET(c10_PRRR)]
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+ str r11, [vcpu, #CP15_OFFSET(c10_NMRR)]
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+ str r12, [vcpu, #CP15_OFFSET(c0_CSSELR)]
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+ .endif
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+
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+ mrc p15, 0, r2, c13, c0, 1 @ CID
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+ mrc p15, 0, r3, c13, c0, 2 @ TID_URW
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+ mrc p15, 0, r4, c13, c0, 3 @ TID_URO
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+ mrc p15, 0, r5, c13, c0, 4 @ TID_PRIV
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+ mrc p15, 0, r6, c5, c0, 0 @ DFSR
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+ mrc p15, 0, r7, c5, c0, 1 @ IFSR
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+ mrc p15, 0, r8, c5, c1, 0 @ ADFSR
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+ mrc p15, 0, r9, c5, c1, 1 @ AIFSR
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+ mrc p15, 0, r10, c6, c0, 0 @ DFAR
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+ mrc p15, 0, r11, c6, c0, 2 @ IFAR
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+ mrc p15, 0, r12, c12, c0, 0 @ VBAR
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+
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+ .if \store_to_vcpu == 0
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+ push {r2-r12} @ Push CP15 registers
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+ .else
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+ str r2, [vcpu, #CP15_OFFSET(c13_CID)]
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+ str r3, [vcpu, #CP15_OFFSET(c13_TID_URW)]
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+ str r4, [vcpu, #CP15_OFFSET(c13_TID_URO)]
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+ str r5, [vcpu, #CP15_OFFSET(c13_TID_PRIV)]
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+ str r6, [vcpu, #CP15_OFFSET(c5_DFSR)]
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+ str r7, [vcpu, #CP15_OFFSET(c5_IFSR)]
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+ str r8, [vcpu, #CP15_OFFSET(c5_ADFSR)]
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+ str r9, [vcpu, #CP15_OFFSET(c5_AIFSR)]
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+ str r10, [vcpu, #CP15_OFFSET(c6_DFAR)]
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+ str r11, [vcpu, #CP15_OFFSET(c6_IFAR)]
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+ str r12, [vcpu, #CP15_OFFSET(c12_VBAR)]
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+ .endif
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+.endm
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+
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+/*
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+ * Reads cp15 registers from memory and writes them to hardware
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+ * @read_from_vcpu: If 0, registers are read in-order from the stack,
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+ * otherwise from the VCPU struct pointed to by vcpup
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+ *
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+ * Assumes vcpu pointer in vcpu reg
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+ */
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+.macro write_cp15_state read_from_vcpu
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+ .if \read_from_vcpu == 0
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+ pop {r2-r12}
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+ .else
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+ ldr r2, [vcpu, #CP15_OFFSET(c13_CID)]
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+ ldr r3, [vcpu, #CP15_OFFSET(c13_TID_URW)]
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+ ldr r4, [vcpu, #CP15_OFFSET(c13_TID_URO)]
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+ ldr r5, [vcpu, #CP15_OFFSET(c13_TID_PRIV)]
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+ ldr r6, [vcpu, #CP15_OFFSET(c5_DFSR)]
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+ ldr r7, [vcpu, #CP15_OFFSET(c5_IFSR)]
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+ ldr r8, [vcpu, #CP15_OFFSET(c5_ADFSR)]
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+ ldr r9, [vcpu, #CP15_OFFSET(c5_AIFSR)]
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+ ldr r10, [vcpu, #CP15_OFFSET(c6_DFAR)]
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+ ldr r11, [vcpu, #CP15_OFFSET(c6_IFAR)]
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+ ldr r12, [vcpu, #CP15_OFFSET(c12_VBAR)]
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+ .endif
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+
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+ mcr p15, 0, r2, c13, c0, 1 @ CID
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+ mcr p15, 0, r3, c13, c0, 2 @ TID_URW
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+ mcr p15, 0, r4, c13, c0, 3 @ TID_URO
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+ mcr p15, 0, r5, c13, c0, 4 @ TID_PRIV
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+ mcr p15, 0, r6, c5, c0, 0 @ DFSR
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+ mcr p15, 0, r7, c5, c0, 1 @ IFSR
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+ mcr p15, 0, r8, c5, c1, 0 @ ADFSR
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+ mcr p15, 0, r9, c5, c1, 1 @ AIFSR
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+ mcr p15, 0, r10, c6, c0, 0 @ DFAR
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+ mcr p15, 0, r11, c6, c0, 2 @ IFAR
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+ mcr p15, 0, r12, c12, c0, 0 @ VBAR
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+
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+ .if \read_from_vcpu == 0
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+ pop {r2-r12}
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+ .else
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+ ldr r2, [vcpu, #CP15_OFFSET(c1_SCTLR)]
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+ ldr r3, [vcpu, #CP15_OFFSET(c1_CPACR)]
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+ ldr r4, [vcpu, #CP15_OFFSET(c2_TTBCR)]
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+ ldr r5, [vcpu, #CP15_OFFSET(c3_DACR)]
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+ add r12, vcpu, #CP15_OFFSET(c2_TTBR0)
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+ ldrd r6, r7, [r12]
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+ add r12, vcpu, #CP15_OFFSET(c2_TTBR1)
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+ ldrd r8, r9, [r12]
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+ ldr r10, [vcpu, #CP15_OFFSET(c10_PRRR)]
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+ ldr r11, [vcpu, #CP15_OFFSET(c10_NMRR)]
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+ ldr r12, [vcpu, #CP15_OFFSET(c0_CSSELR)]
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+ .endif
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+
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+ mcr p15, 0, r2, c1, c0, 0 @ SCTLR
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+ mcr p15, 0, r3, c1, c0, 2 @ CPACR
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+ mcr p15, 0, r4, c2, c0, 2 @ TTBCR
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+ mcr p15, 0, r5, c3, c0, 0 @ DACR
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+ mcrr p15, 0, r6, r7, c2 @ TTBR 0
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+ mcrr p15, 1, r8, r9, c2 @ TTBR 1
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+ mcr p15, 0, r10, c10, c2, 0 @ PRRR
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+ mcr p15, 0, r11, c10, c2, 1 @ NMRR
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+ mcr p15, 2, r12, c0, c0, 0 @ CSSELR
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+.endm
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+
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+/*
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+ * Save the VGIC CPU state into memory
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+ *
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+ * Assumes vcpu pointer in vcpu reg
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+ */
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+.macro save_vgic_state
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+.endm
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+
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+/*
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+ * Restore the VGIC CPU state from memory
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+ *
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+ * Assumes vcpu pointer in vcpu reg
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+ */
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+.macro restore_vgic_state
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+.endm
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+
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+.equ vmentry, 0
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+.equ vmexit, 1
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+
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+/* Configures the HSTR (Hyp System Trap Register) on entry/return
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+ * (hardware reset value is 0) */
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+.macro set_hstr operation
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+ mrc p15, 4, r2, c1, c1, 3
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+ ldr r3, =HSTR_T(15)
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+ .if \operation == vmentry
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+ orr r2, r2, r3 @ Trap CR{15}
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+ .else
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+ bic r2, r2, r3 @ Don't trap any CRx accesses
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+ .endif
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+ mcr p15, 4, r2, c1, c1, 3
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+.endm
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+
|
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+/* Configures the HCPTR (Hyp Coprocessor Trap Register) on entry/return
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+ * (hardware reset value is 0). Keep previous value in r2. */
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+.macro set_hcptr operation, mask
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+ mrc p15, 4, r2, c1, c1, 2
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+ ldr r3, =\mask
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+ .if \operation == vmentry
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+ orr r3, r2, r3 @ Trap coproc-accesses defined in mask
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+ .else
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+ bic r3, r2, r3 @ Don't trap defined coproc-accesses
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|
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+ .endif
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+ mcr p15, 4, r3, c1, c1, 2
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|
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+.endm
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+
|
|
|
+/* Configures the HDCR (Hyp Debug Configuration Register) on entry/return
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|
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+ * (hardware reset value is 0) */
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+.macro set_hdcr operation
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+ mrc p15, 4, r2, c1, c1, 1
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+ ldr r3, =(HDCR_TPM|HDCR_TPMCR)
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|
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+ .if \operation == vmentry
|
|
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+ orr r2, r2, r3 @ Trap some perfmon accesses
|
|
|
+ .else
|
|
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+ bic r2, r2, r3 @ Don't trap any perfmon accesses
|
|
|
+ .endif
|
|
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+ mcr p15, 4, r2, c1, c1, 1
|
|
|
+.endm
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+
|
|
|
+/* Enable/Disable: stage-2 trans., trap interrupts, trap wfi, trap smc */
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|
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+.macro configure_hyp_role operation
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|
|
+ mrc p15, 4, r2, c1, c1, 0 @ HCR
|
|
|
+ bic r2, r2, #HCR_VIRT_EXCP_MASK
|
|
|
+ ldr r3, =HCR_GUEST_MASK
|
|
|
+ .if \operation == vmentry
|
|
|
+ orr r2, r2, r3
|
|
|
+ ldr r3, [vcpu, #VCPU_IRQ_LINES]
|
|
|
+ orr r2, r2, r3
|
|
|
+ .else
|
|
|
+ bic r2, r2, r3
|
|
|
+ .endif
|
|
|
+ mcr p15, 4, r2, c1, c1, 0
|
|
|
+.endm
|
|
|
+
|
|
|
+.macro load_vcpu
|
|
|
+ mrc p15, 4, vcpu, c13, c0, 2 @ HTPIDR
|
|
|
+.endm
|
Christoffer Dall