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@@ -2044,9 +2044,20 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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WREG32(HDP_ADDR_CONFIG, gb_addr_config);
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WREG32(DMA_TILING_CONFIG, gb_addr_config);
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- tmp = gb_addr_config & NUM_PIPES_MASK;
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- tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
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- EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
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+ if ((rdev->config.evergreen.max_backends == 1) &&
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+ (rdev->flags & RADEON_IS_IGP)) {
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+ if ((disabled_rb_mask & 3) == 1) {
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+ /* RB0 disabled, RB1 enabled */
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+ tmp = 0x11111111;
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+ } else {
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+ /* RB1 disabled, RB0 enabled */
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+ tmp = 0x00000000;
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+ }
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+ } else {
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+ tmp = gb_addr_config & NUM_PIPES_MASK;
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+ tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
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+ EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
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+ }
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WREG32(GB_BACKEND_MAP, tmp);
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WREG32(CGTS_SYS_TCC_DISABLE, 0);
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