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@@ -1763,29 +1763,52 @@ static struct spear_function can1_function = {
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.ngroups = ARRAY_SIZE(can1_grps),
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};
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-/* Pad multiplexing for pci device */
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-static const unsigned pci_sata_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18,
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+/* Pad multiplexing for (ras-ip) pci device */
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+static const unsigned pci_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18,
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19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
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37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
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55, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 };
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-#define PCI_SATA_MUXREG \
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- { \
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- .reg = PAD_FUNCTION_EN_0, \
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- .mask = PMX_MCI_DATA8_15_MASK, \
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- .val = 0, \
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- }, { \
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- .reg = PAD_FUNCTION_EN_1, \
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- .mask = PMX_PCI_REG1_MASK, \
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- .val = 0, \
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- }, { \
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- .reg = PAD_FUNCTION_EN_2, \
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- .mask = PMX_PCI_REG2_MASK, \
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- .val = 0, \
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- }
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-/* pad multiplexing for pcie0 device */
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+static struct spear_muxreg pci_muxreg[] = {
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+ {
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+ .reg = PAD_FUNCTION_EN_0,
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+ .mask = PMX_MCI_DATA8_15_MASK,
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+ .val = 0,
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+ }, {
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+ .reg = PAD_FUNCTION_EN_1,
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+ .mask = PMX_PCI_REG1_MASK,
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+ .val = 0,
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+ }, {
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+ .reg = PAD_FUNCTION_EN_2,
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+ .mask = PMX_PCI_REG2_MASK,
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+ .val = 0,
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+ },
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+};
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+
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+static struct spear_modemux pci_modemux[] = {
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+ {
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+ .muxregs = pci_muxreg,
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+ .nmuxregs = ARRAY_SIZE(pci_muxreg),
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+ },
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+};
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+
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+static struct spear_pingroup pci_pingroup = {
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+ .name = "pci_grp",
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+ .pins = pci_pins,
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+ .npins = ARRAY_SIZE(pci_pins),
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+ .modemuxs = pci_modemux,
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+ .nmodemuxs = ARRAY_SIZE(pci_modemux),
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+};
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+
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+static const char *const pci_grps[] = { "pci_grp" };
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+static struct spear_function pci_function = {
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+ .name = "pci",
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+ .groups = pci_grps,
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+ .ngroups = ARRAY_SIZE(pci_grps),
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+};
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+
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+/* pad multiplexing for (fix-part) pcie0 device */
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static struct spear_muxreg pcie0_muxreg[] = {
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- PCI_SATA_MUXREG,
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{
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.reg = PCIE_SATA_CFG,
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.mask = PCIE_CFG_VAL(0),
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@@ -1802,15 +1825,12 @@ static struct spear_modemux pcie0_modemux[] = {
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static struct spear_pingroup pcie0_pingroup = {
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.name = "pcie0_grp",
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- .pins = pci_sata_pins,
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- .npins = ARRAY_SIZE(pci_sata_pins),
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.modemuxs = pcie0_modemux,
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.nmodemuxs = ARRAY_SIZE(pcie0_modemux),
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};
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-/* pad multiplexing for pcie1 device */
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+/* pad multiplexing for (fix-part) pcie1 device */
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static struct spear_muxreg pcie1_muxreg[] = {
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- PCI_SATA_MUXREG,
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{
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.reg = PCIE_SATA_CFG,
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.mask = PCIE_CFG_VAL(1),
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@@ -1827,15 +1847,12 @@ static struct spear_modemux pcie1_modemux[] = {
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static struct spear_pingroup pcie1_pingroup = {
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.name = "pcie1_grp",
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- .pins = pci_sata_pins,
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- .npins = ARRAY_SIZE(pci_sata_pins),
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.modemuxs = pcie1_modemux,
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.nmodemuxs = ARRAY_SIZE(pcie1_modemux),
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};
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-/* pad multiplexing for pcie2 device */
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+/* pad multiplexing for (fix-part) pcie2 device */
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static struct spear_muxreg pcie2_muxreg[] = {
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- PCI_SATA_MUXREG,
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{
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.reg = PCIE_SATA_CFG,
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.mask = PCIE_CFG_VAL(2),
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@@ -1852,22 +1869,20 @@ static struct spear_modemux pcie2_modemux[] = {
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static struct spear_pingroup pcie2_pingroup = {
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.name = "pcie2_grp",
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- .pins = pci_sata_pins,
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- .npins = ARRAY_SIZE(pci_sata_pins),
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.modemuxs = pcie2_modemux,
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.nmodemuxs = ARRAY_SIZE(pcie2_modemux),
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};
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-static const char *const pci_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp" };
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-static struct spear_function pci_function = {
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- .name = "pci",
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- .groups = pci_grps,
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- .ngroups = ARRAY_SIZE(pci_grps),
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+static const char *const pcie_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp"
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+};
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+static struct spear_function pcie_function = {
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+ .name = "pci_express",
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+ .groups = pcie_grps,
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+ .ngroups = ARRAY_SIZE(pcie_grps),
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};
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/* pad multiplexing for sata0 device */
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static struct spear_muxreg sata0_muxreg[] = {
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- PCI_SATA_MUXREG,
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{
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.reg = PCIE_SATA_CFG,
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.mask = SATA_CFG_VAL(0),
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@@ -1884,15 +1899,12 @@ static struct spear_modemux sata0_modemux[] = {
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static struct spear_pingroup sata0_pingroup = {
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.name = "sata0_grp",
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- .pins = pci_sata_pins,
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- .npins = ARRAY_SIZE(pci_sata_pins),
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.modemuxs = sata0_modemux,
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.nmodemuxs = ARRAY_SIZE(sata0_modemux),
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};
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/* pad multiplexing for sata1 device */
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static struct spear_muxreg sata1_muxreg[] = {
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- PCI_SATA_MUXREG,
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{
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.reg = PCIE_SATA_CFG,
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.mask = SATA_CFG_VAL(1),
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@@ -1909,15 +1921,12 @@ static struct spear_modemux sata1_modemux[] = {
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static struct spear_pingroup sata1_pingroup = {
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.name = "sata1_grp",
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- .pins = pci_sata_pins,
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- .npins = ARRAY_SIZE(pci_sata_pins),
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.modemuxs = sata1_modemux,
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.nmodemuxs = ARRAY_SIZE(sata1_modemux),
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};
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/* pad multiplexing for sata2 device */
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static struct spear_muxreg sata2_muxreg[] = {
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- PCI_SATA_MUXREG,
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{
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.reg = PCIE_SATA_CFG,
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.mask = SATA_CFG_VAL(2),
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@@ -1934,8 +1943,6 @@ static struct spear_modemux sata2_modemux[] = {
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static struct spear_pingroup sata2_pingroup = {
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.name = "sata2_grp",
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- .pins = pci_sata_pins,
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- .npins = ARRAY_SIZE(pci_sata_pins),
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.modemuxs = sata2_modemux,
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.nmodemuxs = ARRAY_SIZE(sata2_modemux),
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};
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@@ -2093,6 +2100,7 @@ static struct spear_pingroup *spear1310_pingroups[] = {
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&can0_dis_sd_pingroup,
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&can1_dis_sd_pingroup,
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&can1_dis_kbd_pingroup,
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+ &pci_pingroup,
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&pcie0_pingroup,
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&pcie1_pingroup,
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&pcie2_pingroup,
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@@ -2138,6 +2146,7 @@ static struct spear_function *spear1310_functions[] = {
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&can0_function,
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&can1_function,
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&pci_function,
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+ &pcie_function,
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&sata_function,
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&ssp1_function,
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&gpt64_function,
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