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@@ -724,7 +724,7 @@
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#define MV643XX_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
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#define MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
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#define MV643XX_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
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-#define MV643XX_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)
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+#define MV643XX_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10))
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#define MV643XX_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
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#define MV643XX_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
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#define MV643XX_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
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@@ -1135,7 +1135,7 @@ struct mv64xxx_i2c_pdata {
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#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_1 (1<<19)
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#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_2 (1<<20)
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#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_3 ((1<<20) | (1<<19))
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-#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_4 ((1<<21)
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+#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_4 (1<<21)
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#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_5 ((1<<21) | (1<<19))
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#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_6 ((1<<21) | (1<<20))
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#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_7 ((1<<21) | (1<<20) | (1<<19))
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