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@@ -31,10 +31,10 @@ void cx18_log_statistics(struct cx18 *cx)
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if (!(cx18_debug & CX18_DBGFLG_INFO))
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return;
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- for (i = 0; i <= CX18_MAX_MMIO_RETRIES; i++)
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+ for (i = 0; i <= CX18_MAX_MMIO_WR_RETRIES; i++)
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CX18_DEBUG_INFO("retried_write[%d] = %d\n", i,
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atomic_read(&cx->mmio_stats.retried_write[i]));
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- for (i = 0; i <= CX18_MAX_MMIO_RETRIES; i++)
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+ for (i = 0; i <= CX18_MAX_MMIO_RD_RETRIES; i++)
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CX18_DEBUG_INFO("retried_read[%d] = %d\n", i,
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atomic_read(&cx->mmio_stats.retried_read[i]));
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return;
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@@ -43,7 +43,7 @@ void cx18_log_statistics(struct cx18 *cx)
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void cx18_raw_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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int i;
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- for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
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+ for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
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cx18_raw_writel_noretry(cx, val, addr);
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if (val == cx18_raw_readl_noretry(cx, addr))
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break;
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@@ -55,7 +55,7 @@ u32 cx18_raw_readl_retry(struct cx18 *cx, const void __iomem *addr)
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{
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int i;
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u32 val;
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- for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
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+ for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
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val = cx18_raw_readl_noretry(cx, addr);
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if (val != 0xffffffff) /* PCI bus read error */
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break;
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@@ -68,7 +68,7 @@ u16 cx18_raw_readw_retry(struct cx18 *cx, const void __iomem *addr)
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{
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int i;
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u16 val;
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- for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
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+ for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
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val = cx18_raw_readw_noretry(cx, addr);
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if (val != 0xffff) /* PCI bus read error */
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break;
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@@ -80,7 +80,7 @@ u16 cx18_raw_readw_retry(struct cx18 *cx, const void __iomem *addr)
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void cx18_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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int i;
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- for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
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+ for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
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cx18_writel_noretry(cx, val, addr);
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if (val == cx18_readl_noretry(cx, addr))
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break;
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@@ -93,7 +93,7 @@ void _cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr,
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{
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int i;
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eval &= mask;
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- for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
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+ for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
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cx18_writel_noretry(cx, val, addr);
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if (eval == (cx18_readl_noretry(cx, addr) & mask))
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break;
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@@ -104,7 +104,7 @@ void _cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr,
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void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr)
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{
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int i;
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- for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
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+ for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
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cx18_writew_noretry(cx, val, addr);
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if (val == cx18_readw_noretry(cx, addr))
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break;
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@@ -115,7 +115,7 @@ void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr)
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void cx18_writeb_retry(struct cx18 *cx, u8 val, void __iomem *addr)
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{
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int i;
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- for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
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+ for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
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cx18_writeb_noretry(cx, val, addr);
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if (val == cx18_readb_noretry(cx, addr))
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break;
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@@ -127,7 +127,7 @@ u32 cx18_readl_retry(struct cx18 *cx, const void __iomem *addr)
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{
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int i;
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u32 val;
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- for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
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+ for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
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val = cx18_readl_noretry(cx, addr);
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if (val != 0xffffffff) /* PCI bus read error */
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break;
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@@ -140,7 +140,7 @@ u16 cx18_readw_retry(struct cx18 *cx, const void __iomem *addr)
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{
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int i;
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u16 val;
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- for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
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+ for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
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val = cx18_readw_noretry(cx, addr);
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if (val != 0xffff) /* PCI bus read error */
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break;
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@@ -153,7 +153,7 @@ u8 cx18_readb_retry(struct cx18 *cx, const void __iomem *addr)
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{
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int i;
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u8 val;
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- for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
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+ for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
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val = cx18_readb_noretry(cx, addr);
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if (val != 0xff) /* PCI bus read error */
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break;
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