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+/*
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+ * omap_cf.c -- OMAP 16xx CompactFlash controller driver
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+ *
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+ * Copyright (c) 2005 David Brownell
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/kernel.h>
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+#include <linux/sched.h>
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+#include <linux/device.h>
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+#include <linux/errno.h>
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+#include <linux/init.h>
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+#include <linux/delay.h>
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+#include <linux/interrupt.h>
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+
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+#include <pcmcia/ss.h>
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+
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+#include <asm/hardware.h>
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+#include <asm/io.h>
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+#include <asm/mach-types.h>
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+#include <asm/sizes.h>
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+
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+#include <asm/arch/mux.h>
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+#include <asm/arch/tc.h>
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+
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+
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+/* NOTE: don't expect this to support many I/O cards. The 16xx chips have
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+ * hard-wired timings to support Compact Flash memory cards; they won't work
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+ * with various other devices (like WLAN adapters) without some external
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+ * logic to help out.
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+ *
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+ * NOTE: CF controller docs disagree with address space docs as to where
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+ * CF_BASE really lives; this is a doc erratum.
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+ */
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+#define CF_BASE 0xfffe2800
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+
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+/* status; read after IRQ */
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+#define CF_STATUS_REG __REG16(CF_BASE + 0x00)
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+# define CF_STATUS_BAD_READ (1 << 2)
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+# define CF_STATUS_BAD_WRITE (1 << 1)
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+# define CF_STATUS_CARD_DETECT (1 << 0)
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+
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+/* which chipselect (CS0..CS3) is used for CF (active low) */
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+#define CF_CFG_REG __REG16(CF_BASE + 0x02)
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+
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+/* card reset */
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+#define CF_CONTROL_REG __REG16(CF_BASE + 0x04)
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+# define CF_CONTROL_RESET (1 << 0)
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+
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+#define omap_cf_present() (!(CF_STATUS_REG & CF_STATUS_CARD_DETECT))
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+
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+/*--------------------------------------------------------------------------*/
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+
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+static const char driver_name[] = "omap_cf";
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+
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+struct omap_cf_socket {
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+ struct pcmcia_socket socket;
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+
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+ struct timer_list timer;
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+ unsigned present:1;
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+ unsigned active:1;
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+
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+ struct platform_device *pdev;
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+ unsigned long phys_cf;
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+ u_int irq;
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+};
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+
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+#define POLL_INTERVAL (2 * HZ)
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+
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+#define SZ_2K (2 * SZ_1K)
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+
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+/*--------------------------------------------------------------------------*/
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+
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+static int omap_cf_ss_init(struct pcmcia_socket *s)
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+{
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+ return 0;
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+}
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+
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+/* the timer is primarily to kick this socket's pccardd */
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+static void omap_cf_timer(unsigned long _cf)
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+{
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+ struct omap_cf_socket *cf = (void *) _cf;
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+ unsigned present = omap_cf_present();
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+
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+ if (present != cf->present) {
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+ cf->present = present;
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+ pr_debug("%s: card %s\n", driver_name,
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+ present ? "present" : "gone");
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+ pcmcia_parse_events(&cf->socket, SS_DETECT);
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+ }
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+
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+ if (cf->active)
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+ mod_timer(&cf->timer, jiffies + POLL_INTERVAL);
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+}
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+
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+/* This irq handler prevents "irqNNN: nobody cared" messages as drivers
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+ * claim the card's IRQ. It may also detect some card insertions, but
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+ * not removals; it can't always eliminate timer irqs.
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+ */
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+static irqreturn_t omap_cf_irq(int irq, void *_cf, struct pt_regs *r)
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+{
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+ omap_cf_timer((unsigned long)_cf);
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+ return IRQ_HANDLED;
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+}
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+
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+static int omap_cf_get_status(struct pcmcia_socket *s, u_int *sp)
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+{
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+ if (!sp)
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+ return -EINVAL;
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+
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+ /* FIXME power management should probably be board-specific:
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+ * - 3VCARD vs XVCARD (OSK only handles 3VCARD)
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+ * - POWERON (switched on/off by set_socket)
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+ */
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+ if (omap_cf_present()) {
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+ struct omap_cf_socket *cf;
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+
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+ *sp = SS_READY | SS_DETECT | SS_POWERON | SS_3VCARD;
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+ cf = container_of(s, struct omap_cf_socket, socket);
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+ s->irq.AssignedIRQ = cf->irq;
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+ } else
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+ *sp = 0;
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+ return 0;
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+}
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+
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+static int
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+omap_cf_set_socket(struct pcmcia_socket *sock, struct socket_state_t *s)
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+{
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+ u16 control;
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+
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+ /* FIXME some non-OSK boards will support power switching */
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+ switch (s->Vcc) {
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+ case 0:
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+ case 33:
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+ break;
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+ default:
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+ return -EINVAL;
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+ }
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+
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+ control = CF_CONTROL_REG;
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+ if (s->flags & SS_RESET)
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+ CF_CONTROL_REG = CF_CONTROL_RESET;
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+ else
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+ CF_CONTROL_REG = 0;
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+
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+ pr_debug("%s: Vcc %d, io_irq %d, flags %04x csc %04x\n",
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+ driver_name, s->Vcc, s->io_irq, s->flags, s->csc_mask);
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+
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+ return 0;
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+}
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+
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+static int omap_cf_ss_suspend(struct pcmcia_socket *s)
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+{
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+ pr_debug("%s: %s\n", driver_name, __FUNCTION__);
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+ return omap_cf_set_socket(s, &dead_socket);
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+}
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+
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+/* regions are 2K each: mem, attrib, io (and reserved-for-ide) */
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+
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+static int
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+omap_cf_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
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+{
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+ struct omap_cf_socket *cf;
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+
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+ cf = container_of(s, struct omap_cf_socket, socket);
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+ io->flags &= MAP_ACTIVE|MAP_ATTRIB|MAP_16BIT;
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+ io->start = cf->phys_cf + SZ_4K;
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+ io->stop = io->start + SZ_2K - 1;
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+ return 0;
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+}
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+
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+static int
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+omap_cf_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *map)
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+{
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+ struct omap_cf_socket *cf;
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+
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+ if (map->card_start)
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+ return -EINVAL;
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+ cf = container_of(s, struct omap_cf_socket, socket);
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+ map->static_start = cf->phys_cf;
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+ map->flags &= MAP_ACTIVE|MAP_ATTRIB|MAP_16BIT;
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+ if (map->flags & MAP_ATTRIB)
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+ map->static_start += SZ_2K;
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+ return 0;
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+}
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+
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+static struct pccard_operations omap_cf_ops = {
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+ .init = omap_cf_ss_init,
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+ .suspend = omap_cf_ss_suspend,
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+ .get_status = omap_cf_get_status,
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+ .set_socket = omap_cf_set_socket,
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+ .set_io_map = omap_cf_set_io_map,
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+ .set_mem_map = omap_cf_set_mem_map,
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+};
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+
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+/*--------------------------------------------------------------------------*/
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+
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+/*
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+ * NOTE: right now the only board-specific platform_data is
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+ * "what chipselect is used". Boards could want more.
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+ */
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+
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+static int __init omap_cf_probe(struct device *dev)
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+{
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+ unsigned seg;
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+ struct omap_cf_socket *cf;
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+ struct platform_device *pdev = to_platform_device(dev);
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+ int irq;
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+ int status;
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+
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+ seg = (int) dev->platform_data;
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+ if (seg == 0 || seg > 3)
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+ return -ENODEV;
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+
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+ /* either CFLASH.IREQ (INT_1610_CF) or some GPIO */
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+ irq = platform_get_irq(pdev, 0);
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+ if (!irq)
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+ return -EINVAL;
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+
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+ cf = kcalloc(1, sizeof *cf, GFP_KERNEL);
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+ if (!cf)
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+ return -ENOMEM;
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+ init_timer(&cf->timer);
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+ cf->timer.function = omap_cf_timer;
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+ cf->timer.data = (unsigned long) cf;
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+
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+ cf->pdev = pdev;
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+ dev_set_drvdata(dev, cf);
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+
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+ /* this primarily just shuts up irq handling noise */
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+ status = request_irq(irq, omap_cf_irq, SA_SHIRQ,
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+ driver_name, cf);
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+ if (status < 0)
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+ goto fail0;
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+ cf->irq = irq;
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+ cf->socket.pci_irq = irq;
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+
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+ switch (seg) {
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+ /* NOTE: CS0 could be configured too ... */
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+ case 1:
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+ cf->phys_cf = OMAP_CS1_PHYS;
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+ break;
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+ case 2:
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+ cf->phys_cf = OMAP_CS2_PHYS;
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+ break;
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+ case 3:
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+ cf->phys_cf = omap_cs3_phys();
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+ break;
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+ default:
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+ goto fail1;
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+ }
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+
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+ /* pcmcia layer only remaps "real" memory */
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+ cf->socket.io_offset = (unsigned long)
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+ ioremap(cf->phys_cf + SZ_4K, SZ_2K);
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+ if (!cf->socket.io_offset)
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+ goto fail1;
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+
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+ if (!request_mem_region(cf->phys_cf, SZ_8K, driver_name))
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+ goto fail1;
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+
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+ /* NOTE: CF conflicts with MMC1 */
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+ omap_cfg_reg(W11_1610_CF_CD1);
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+ omap_cfg_reg(P11_1610_CF_CD2);
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+ omap_cfg_reg(R11_1610_CF_IOIS16);
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+ omap_cfg_reg(V10_1610_CF_IREQ);
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+ omap_cfg_reg(W10_1610_CF_RESET);
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+
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+ CF_CFG_REG = ~(1 << seg);
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+
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+ pr_info("%s: cs%d on irq %d\n", driver_name, seg, irq);
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+
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+ /* NOTE: better EMIFS setup might support more cards; but the
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+ * TRM only shows how to affect regular flash signals, not their
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+ * CF/PCMCIA variants...
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+ */
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+ pr_debug("%s: cs%d, previous ccs %08x acs %08x\n", driver_name,
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+ seg, EMIFS_CCS(seg), EMIFS_ACS(seg));
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+ EMIFS_CCS(seg) = 0x0004a1b3; /* synch mode 4 etc */
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+ EMIFS_ACS(seg) = 0x00000000; /* OE hold/setup */
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+
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+ /* CF uses armxor_ck, which is "always" available */
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+
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+ pr_debug("%s: sts %04x cfg %04x control %04x %s\n", driver_name,
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+ CF_STATUS_REG, CF_CFG_REG, CF_CONTROL_REG,
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+ omap_cf_present() ? "present" : "(not present)");
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+
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+ cf->socket.owner = THIS_MODULE;
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+ cf->socket.dev.dev = dev;
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+ cf->socket.ops = &omap_cf_ops;
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+ cf->socket.resource_ops = &pccard_static_ops;
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+ cf->socket.features = SS_CAP_PCCARD | SS_CAP_STATIC_MAP
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+ | SS_CAP_MEM_ALIGN;
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+ cf->socket.map_size = SZ_2K;
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+
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+ status = pcmcia_register_socket(&cf->socket);
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+ if (status < 0)
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+ goto fail2;
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+
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+ cf->active = 1;
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+ mod_timer(&cf->timer, jiffies + POLL_INTERVAL);
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+ return 0;
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+
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+fail2:
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+ iounmap((void __iomem *) cf->socket.io_offset);
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+ release_mem_region(cf->phys_cf, SZ_8K);
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+fail1:
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+ free_irq(irq, cf);
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+fail0:
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+ kfree(cf);
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+ return status;
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+}
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+
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+static int __devexit omap_cf_remove(struct device *dev)
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+{
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+ struct omap_cf_socket *cf = dev_get_drvdata(dev);
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+
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+ cf->active = 0;
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+ pcmcia_unregister_socket(&cf->socket);
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+ del_timer_sync(&cf->timer);
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+ iounmap((void __iomem *) cf->socket.io_offset);
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+ release_mem_region(cf->phys_cf, SZ_8K);
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+ free_irq(cf->irq, cf);
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+ kfree(cf);
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+ return 0;
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+}
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+
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+static int omap_cf_suspend(struct device *dev, pm_message_t mesg, u32 level)
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+{
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+ if (level != SUSPEND_SAVE_STATE)
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+ return 0;
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+ return pcmcia_socket_dev_suspend(dev, mesg);
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+}
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+
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+static int omap_cf_resume(struct device *dev, u32 level)
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+{
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+ if (level != RESUME_RESTORE_STATE)
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+ return 0;
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+ return pcmcia_socket_dev_resume(dev);
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+}
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+
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+static struct device_driver omap_cf_driver = {
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+ .name = (char *) driver_name,
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+ .bus = &platform_bus_type,
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+ .probe = omap_cf_probe,
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+ .remove = __devexit_p(omap_cf_remove),
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+ .suspend = omap_cf_suspend,
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+ .resume = omap_cf_resume,
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+};
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+
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+static int __init omap_cf_init(void)
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+{
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+ if (cpu_is_omap16xx())
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+ driver_register(&omap_cf_driver);
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+ return 0;
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+}
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+
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+static void __exit omap_cf_exit(void)
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+{
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+ if (cpu_is_omap16xx())
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+ driver_unregister(&omap_cf_driver);
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+}
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+
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+module_init(omap_cf_init);
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+module_exit(omap_cf_exit);
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+
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+MODULE_DESCRIPTION("OMAP CF Driver");
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+MODULE_LICENSE("GPL");
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