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@@ -372,6 +372,23 @@ struct dio200_region {
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enum dio200_regtype regtype;
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};
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+/*
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+ * Subdevice types.
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+ */
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+enum dio200_sdtype { sd_none, sd_intr, sd_8255, sd_8254, sd_timer };
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+
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+#define DIO200_MAX_SUBDEVS 8
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+#define DIO200_MAX_ISNS 6
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+
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+struct dio200_layout {
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+ unsigned short n_subdevs; /* number of subdevices */
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+ unsigned char sdtype[DIO200_MAX_SUBDEVS]; /* enum dio200_sdtype */
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+ unsigned char sdinfo[DIO200_MAX_SUBDEVS]; /* depends on sdtype */
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+ bool has_int_sce:1; /* has interrupt enable/status reg */
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+ bool has_clk_gat_sce:1; /* has clock/gate selection registers */
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+ bool has_enhancements:1; /* has enhanced features */
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+};
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+
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/*
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* Board descriptions.
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*/
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@@ -386,27 +403,10 @@ enum dio200_pci_model {
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pcie296_model
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};
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-enum dio200_layout_idx {
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-#if DO_ISA
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- pc212_layout,
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- pc214_layout,
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-#endif
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- pc215_layout,
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-#if DO_ISA
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- pc218_layout,
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-#endif
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- pc272_layout,
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-#if DO_PCI
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- pcie215_layout,
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- pcie236_layout,
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- pcie296_layout,
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-#endif
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-};
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-
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struct dio200_board {
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const char *name;
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+ struct dio200_layout layout;
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enum dio200_bustype bustype;
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- enum dio200_layout_idx layout;
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unsigned char mainbar;
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unsigned char mainshift;
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unsigned int mainsize;
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@@ -417,32 +417,61 @@ static const struct dio200_board dio200_isa_boards[] = {
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{
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.name = "pc212e",
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.bustype = isa_bustype,
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- .layout = pc212_layout,
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.mainsize = DIO200_IO_SIZE,
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+ .layout = {
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+ .n_subdevs = 6,
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+ .sdtype = {sd_8255, sd_8254, sd_8254, sd_8254, sd_8254,
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+ sd_intr},
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+ .sdinfo = {0x00, 0x08, 0x0C, 0x10, 0x14, 0x3F},
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+ .has_int_sce = true,
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+ .has_clk_gat_sce = true,
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+ },
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},
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{
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.name = "pc214e",
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.bustype = isa_bustype,
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- .layout = pc214_layout,
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.mainsize = DIO200_IO_SIZE,
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+ .layout = {
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+ .n_subdevs = 4,
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+ .sdtype = {sd_8255, sd_8255, sd_8254, sd_intr},
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+ .sdinfo = {0x00, 0x08, 0x10, 0x01},
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+ },
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},
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{
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.name = "pc215e",
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.bustype = isa_bustype,
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- .layout = pc215_layout,
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.mainsize = DIO200_IO_SIZE,
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+ .layout = {
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+ .n_subdevs = 5,
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+ .sdtype = {sd_8255, sd_8255, sd_8254, sd_8254, sd_intr},
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+ .sdinfo = {0x00, 0x08, 0x10, 0x14, 0x3F},
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+ .has_int_sce = true,
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+ .has_clk_gat_sce = true,
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+ },
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},
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{
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.name = "pc218e",
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.bustype = isa_bustype,
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- .layout = pc218_layout,
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.mainsize = DIO200_IO_SIZE,
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+ .layout = {
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+ .n_subdevs = 7,
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+ .sdtype = {sd_8254, sd_8254, sd_8255, sd_8254, sd_8254,
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+ sd_intr},
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+ .sdinfo = {0x00, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x3F},
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+ .has_int_sce = true,
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+ .has_clk_gat_sce = true,
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+ },
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},
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{
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.name = "pc272e",
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.bustype = isa_bustype,
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- .layout = pc272_layout,
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.mainsize = DIO200_IO_SIZE,
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+ .layout = {
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+ .n_subdevs = 4,
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+ .sdtype = {sd_8255, sd_8255, sd_8255, sd_intr},
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+ .sdinfo = {0x00, 0x08, 0x10, 0x3F},
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+ .has_int_sce = true,
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+ },
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},
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};
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#endif
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@@ -452,148 +481,82 @@ static const struct dio200_board dio200_pci_boards[] = {
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[pci215_model] {
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.name = "pci215",
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.bustype = pci_bustype,
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- .layout = pc215_layout,
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.mainbar = 2,
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.mainsize = DIO200_IO_SIZE,
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+ .layout = {
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+ .n_subdevs = 5,
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+ .sdtype = {sd_8255, sd_8255, sd_8254, sd_8254, sd_intr},
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+ .sdinfo = {0x00, 0x08, 0x10, 0x14, 0x3F},
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+ .has_int_sce = true,
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+ .has_clk_gat_sce = true,
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+ },
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},
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[pci272_model] {
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.name = "pci272",
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.bustype = pci_bustype,
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- .layout = pc272_layout,
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.mainbar = 2,
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.mainsize = DIO200_IO_SIZE,
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+ .layout = {
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+ .n_subdevs = 4,
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+ .sdtype = {sd_8255, sd_8255, sd_8255, sd_intr},
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+ .sdinfo = {0x00, 0x08, 0x10, 0x3F},
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+ .has_int_sce = true,
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+ },
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},
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[pcie215_model] {
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.name = "pcie215",
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.bustype = pci_bustype,
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- .layout = pcie215_layout,
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.mainbar = 1,
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.mainshift = 3,
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.mainsize = DIO200_PCIE_IO_SIZE,
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+ .layout = {
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+ .n_subdevs = 8,
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+ .sdtype = {sd_8255, sd_none, sd_8255, sd_none,
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+ sd_8254, sd_8254, sd_timer, sd_intr},
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+ .sdinfo = {0x00, 0x00, 0x08, 0x00,
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+ 0x10, 0x14, 0x00, 0x3F},
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+ .has_int_sce = true,
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+ .has_clk_gat_sce = true,
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+ .has_enhancements = true,
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+ },
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},
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[pcie236_model] {
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.name = "pcie236",
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.bustype = pci_bustype,
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- .layout = pcie236_layout,
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.mainbar = 1,
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.mainshift = 3,
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.mainsize = DIO200_PCIE_IO_SIZE,
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+ .layout = {
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+ .n_subdevs = 8,
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+ .sdtype = {sd_8255, sd_none, sd_none, sd_none,
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+ sd_8254, sd_8254, sd_timer, sd_intr},
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+ .sdinfo = {0x00, 0x00, 0x00, 0x00,
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+ 0x10, 0x14, 0x00, 0x3F},
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+ .has_int_sce = true,
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+ .has_clk_gat_sce = true,
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+ .has_enhancements = true,
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+ },
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},
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[pcie296_model] {
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.name = "pcie296",
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.bustype = pci_bustype,
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- .layout = pcie296_layout,
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.mainbar = 1,
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.mainshift = 3,
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.mainsize = DIO200_PCIE_IO_SIZE,
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+ .layout = {
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+ .n_subdevs = 8,
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+ .sdtype = {sd_8255, sd_8255, sd_8255, sd_8255,
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+ sd_8254, sd_8254, sd_timer, sd_intr},
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+ .sdinfo = {0x00, 0x04, 0x08, 0x0C,
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+ 0x10, 0x14, 0x00, 0x3F},
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+ .has_int_sce = true,
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+ .has_clk_gat_sce = true,
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+ .has_enhancements = true,
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+ },
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},
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};
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#endif
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-/*
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- * Layout descriptions - some ISA and PCI board descriptions share the same
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- * layout.
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- */
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-
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-enum dio200_sdtype { sd_none, sd_intr, sd_8255, sd_8254, sd_timer };
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-
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-#define DIO200_MAX_SUBDEVS 8
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-#define DIO200_MAX_ISNS 6
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-
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-struct dio200_layout {
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- unsigned short n_subdevs; /* number of subdevices */
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- unsigned char sdtype[DIO200_MAX_SUBDEVS]; /* enum dio200_sdtype */
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- unsigned char sdinfo[DIO200_MAX_SUBDEVS]; /* depends on sdtype */
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- char has_int_sce; /* has interrupt enable/status register */
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- char has_clk_gat_sce; /* has clock/gate selection registers */
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- char has_enhancements; /* has enhanced features */
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-};
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-
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-static const struct dio200_layout dio200_layouts[] = {
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-#if DO_ISA
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- [pc212_layout] = {
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- .n_subdevs = 6,
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- .sdtype = {sd_8255, sd_8254, sd_8254, sd_8254,
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- sd_8254,
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- sd_intr},
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- .sdinfo = {0x00, 0x08, 0x0C, 0x10, 0x14,
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- 0x3F},
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- .has_int_sce = 1,
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- .has_clk_gat_sce = 1,
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- },
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- [pc214_layout] = {
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- .n_subdevs = 4,
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- .sdtype = {sd_8255, sd_8255, sd_8254,
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- sd_intr},
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- .sdinfo = {0x00, 0x08, 0x10, 0x01},
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- .has_int_sce = 0,
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- .has_clk_gat_sce = 0,
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- },
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-#endif
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- [pc215_layout] = {
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- .n_subdevs = 5,
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- .sdtype = {sd_8255, sd_8255, sd_8254,
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- sd_8254,
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- sd_intr},
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- .sdinfo = {0x00, 0x08, 0x10, 0x14, 0x3F},
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- .has_int_sce = 1,
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- .has_clk_gat_sce = 1,
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- },
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-#if DO_ISA
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- [pc218_layout] = {
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- .n_subdevs = 7,
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- .sdtype = {sd_8254, sd_8254, sd_8255, sd_8254,
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- sd_8254,
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- sd_intr},
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- .sdinfo = {0x00, 0x04, 0x08, 0x0C, 0x10,
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- 0x14,
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- 0x3F},
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- .has_int_sce = 1,
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- .has_clk_gat_sce = 1,
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- },
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-#endif
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- [pc272_layout] = {
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- .n_subdevs = 4,
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- .sdtype = {sd_8255, sd_8255, sd_8255,
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- sd_intr},
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- .sdinfo = {0x00, 0x08, 0x10, 0x3F},
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- .has_int_sce = 1,
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- .has_clk_gat_sce = 0,
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- },
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-#if DO_PCI
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- [pcie215_layout] = {
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- .n_subdevs = 8,
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- .sdtype = {sd_8255, sd_none, sd_8255, sd_none,
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- sd_8254, sd_8254, sd_timer, sd_intr},
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- .sdinfo = {0x00, 0x00, 0x08, 0x00,
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- 0x10, 0x14, 0x00, 0x3F},
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- .has_int_sce = 1,
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- .has_clk_gat_sce = 1,
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- .has_enhancements = 1,
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- },
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- [pcie236_layout] = {
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- .n_subdevs = 8,
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- .sdtype = {sd_8255, sd_none, sd_none, sd_none,
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- sd_8254, sd_8254, sd_timer, sd_intr},
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- .sdinfo = {0x00, 0x00, 0x00, 0x00,
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- 0x10, 0x14, 0x00, 0x3F},
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- .has_int_sce = 1,
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- .has_clk_gat_sce = 1,
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- .has_enhancements = 1,
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- },
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- [pcie296_layout] = {
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- .n_subdevs = 8,
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- .sdtype = {sd_8255, sd_8255, sd_8255, sd_8255,
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- sd_8254, sd_8254, sd_timer, sd_intr},
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- .sdinfo = {0x00, 0x04, 0x08, 0x0C,
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- 0x10, 0x14, 0x00, 0x3F},
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- .has_int_sce = 1,
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- .has_clk_gat_sce = 1,
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- .has_enhancements = 1,
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- },
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-#endif
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-};
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-
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/* this structure is for data unique to this hardware driver. If
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several hardware drivers keep similar information in this structure,
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feel free to suggest moving the variable to the struct comedi_device struct.
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@@ -630,7 +593,7 @@ struct dio200_subdev_intr {
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static inline const struct dio200_layout *
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dio200_board_layout(const struct dio200_board *board)
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{
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- return &dio200_layouts[board->layout];
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+ return &board->layout;
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}
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static inline const struct dio200_layout *
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