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@@ -41,7 +41,7 @@
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* | dss_cache |
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* +--------------------+
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* v
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- * configure()
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+ * write_regs()
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* v
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* +--------------------+
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* | shadow registers |
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@@ -237,65 +237,63 @@ int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl)
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return r;
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}
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-static int configure_overlay(enum omap_plane plane)
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+static int dss_ovl_write_regs(struct omap_overlay *ovl)
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{
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- struct omap_overlay *ovl;
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struct overlay_cache_data *c;
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struct omap_overlay_info *oi;
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bool ilace, replication;
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int r;
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- DSSDBGF("%d", plane);
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+ DSSDBGF("%d", ovl->id);
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- c = &dss_cache.overlay_cache[plane];
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+ c = &dss_cache.overlay_cache[ovl->id];
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oi = &c->info;
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if (!c->enabled) {
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- dispc_ovl_enable(plane, 0);
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+ dispc_ovl_enable(ovl->id, 0);
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return 0;
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}
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- ovl = omap_dss_get_overlay(plane);
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-
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replication = dss_use_replication(ovl->manager->device, oi->color_mode);
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ilace = ovl->manager->device->type == OMAP_DISPLAY_TYPE_VENC;
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- dispc_ovl_set_channel_out(plane, c->channel);
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+ dispc_ovl_set_channel_out(ovl->id, c->channel);
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- r = dispc_ovl_setup(plane, oi, ilace, replication);
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+ r = dispc_ovl_setup(ovl->id, oi, ilace, replication);
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if (r) {
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/* this shouldn't happen */
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- DSSERR("dispc_ovl_setup failed for ovl %d\n", plane);
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- dispc_ovl_enable(plane, 0);
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+ DSSERR("dispc_ovl_setup failed for ovl %d\n", ovl->id);
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+ dispc_ovl_enable(ovl->id, 0);
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return r;
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}
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- dispc_ovl_set_fifo_threshold(plane, c->fifo_low, c->fifo_high);
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+ dispc_ovl_set_fifo_threshold(ovl->id, c->fifo_low, c->fifo_high);
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- dispc_ovl_enable(plane, 1);
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+ dispc_ovl_enable(ovl->id, 1);
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return 0;
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}
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-static void configure_manager(enum omap_channel channel)
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+static void dss_mgr_write_regs(struct omap_overlay_manager *mgr)
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{
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struct omap_overlay_manager_info *mi;
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- DSSDBGF("%d", channel);
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+ DSSDBGF("%d", mgr->id);
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- /* picking info from the cache */
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- mi = &dss_cache.manager_cache[channel].info;
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+ mi = &dss_cache.manager_cache[mgr->id].info;
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- dispc_mgr_setup(channel, mi);
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+ dispc_mgr_setup(mgr->id, mi);
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}
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-/* configure_dispc() tries to write values from cache to shadow registers.
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+/* dss_write_regs() tries to write values from cache to shadow registers.
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* It writes only to those managers/overlays that are not busy.
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* returns 0 if everything could be written to shadow registers.
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* returns 1 if not everything could be written to shadow registers. */
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-static int configure_dispc(void)
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+static int dss_write_regs(void)
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{
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+ struct omap_overlay *ovl;
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+ struct omap_overlay_manager *mgr;
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struct overlay_cache_data *oc;
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struct manager_cache_data *mc;
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const int num_ovls = dss_feat_get_num_ovls();
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@@ -316,6 +314,7 @@ static int configure_dispc(void)
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/* Commit overlay settings */
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for (i = 0; i < num_ovls; ++i) {
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+ ovl = omap_dss_get_overlay(i);
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oc = &dss_cache.overlay_cache[i];
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mc = &dss_cache.manager_cache[oc->channel];
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@@ -330,9 +329,9 @@ static int configure_dispc(void)
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continue;
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}
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- r = configure_overlay(i);
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+ r = dss_ovl_write_regs(ovl);
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if (r)
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- DSSERR("configure_overlay %d failed\n", i);
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+ DSSERR("dss_ovl_write_regs %d failed\n", i);
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oc->dirty = false;
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oc->shadow_dirty = true;
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@@ -341,6 +340,7 @@ static int configure_dispc(void)
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/* Commit manager settings */
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for (i = 0; i < num_mgrs; ++i) {
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+ mgr = omap_dss_get_overlay_manager(i);
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mc = &dss_cache.manager_cache[i];
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if (!mc->dirty)
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@@ -354,7 +354,7 @@ static int configure_dispc(void)
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continue;
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}
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- configure_manager(i);
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+ dss_mgr_write_regs(mgr);
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mc->dirty = false;
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mc->shadow_dirty = true;
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mgr_go[i] = true;
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@@ -391,7 +391,7 @@ void dss_mgr_start_update(struct omap_overlay_manager *mgr)
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mc = &dss_cache.manager_cache[mgr->id];
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mc->do_manual_update = true;
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- configure_dispc();
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+ dss_write_regs();
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mc->do_manual_update = false;
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list_for_each_entry(ovl, &mgr->overlays, list) {
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@@ -465,7 +465,7 @@ static void dss_apply_irq_handler(void *data, u32 mask)
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mc->shadow_dirty = false;
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}
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- r = configure_dispc();
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+ r = dss_write_regs();
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if (r == 1)
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goto end;
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@@ -623,7 +623,7 @@ int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
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if (!dss_cache.irq_enabled)
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dss_register_vsync_isr();
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- configure_dispc();
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+ dss_write_regs();
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}
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spin_unlock_irqrestore(&dss_cache.lock, flags);
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