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@@ -600,49 +600,17 @@ static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
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}
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}
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}
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}
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-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
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-static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
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-{
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- u32 tmp;
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-
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- if (dev->phy.type != B43_PHYTYPE_N)
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- return;
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-
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- switch (dev->dev->bus_type) {
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-#ifdef CONFIG_B43_BCMA
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- case B43_BUS_BCMA:
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- tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
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- if (force)
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- tmp |= BCMA_IOCTL_FGC;
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- else
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- tmp &= ~BCMA_IOCTL_FGC;
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- bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
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- break;
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-#endif
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-#ifdef CONFIG_B43_SSB
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- case B43_BUS_SSB:
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- tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
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- if (force)
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- tmp |= SSB_TMSLOW_FGC;
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- else
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- tmp &= ~SSB_TMSLOW_FGC;
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- ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
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- break;
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-#endif
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- }
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-}
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-
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/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
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/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
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static void b43_nphy_reset_cca(struct b43_wldev *dev)
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static void b43_nphy_reset_cca(struct b43_wldev *dev)
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{
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{
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u16 bbcfg;
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u16 bbcfg;
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- b43_nphy_bmac_clock_fgc(dev, 1);
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+ b43_phy_force_clock(dev, 1);
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bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
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bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
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b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
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b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
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udelay(1);
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udelay(1);
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b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
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b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
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- b43_nphy_bmac_clock_fgc(dev, 0);
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+ b43_phy_force_clock(dev, 0);
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b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
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b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
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}
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}
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@@ -3715,11 +3683,11 @@ int b43_phy_initn(struct b43_wldev *dev)
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b43_nphy_workarounds(dev);
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b43_nphy_workarounds(dev);
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/* Reset CCA, in init code it differs a little from standard way */
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/* Reset CCA, in init code it differs a little from standard way */
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- b43_nphy_bmac_clock_fgc(dev, 1);
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+ b43_phy_force_clock(dev, 1);
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tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
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tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
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b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
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b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
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b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
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b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
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- b43_nphy_bmac_clock_fgc(dev, 0);
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+ b43_phy_force_clock(dev, 0);
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b43_mac_phy_clock_set(dev, true);
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b43_mac_phy_clock_set(dev, true);
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