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@@ -94,6 +94,7 @@ static struct _intel_private {
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struct pci_dev *pcidev; /* device one */
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struct pci_dev *bridge_dev;
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u8 __iomem *registers;
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+ phys_addr_t gtt_bus_addr;
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u32 __iomem *gtt; /* I915G */
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int num_dcache_entries;
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union {
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@@ -799,10 +800,27 @@ static unsigned int intel_gtt_mappable_entries(void)
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static int intel_gtt_init(void)
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{
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+ u32 gtt_map_size;
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+
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+ intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
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+ intel_private.base.gtt_total_entries = intel_gtt_total_entries();
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+
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+ gtt_map_size = intel_private.base.gtt_total_entries * 4;
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+
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+ intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
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+ gtt_map_size);
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+ if (!intel_private.gtt) {
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+ iounmap(intel_private.registers);
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+ return -ENOMEM;
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+ }
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+
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+ global_cache_flush(); /* FIXME: ? */
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+
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/* we have to call this as early as possible after the MMIO base address is known */
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intel_private.base.gtt_stolen_entries = intel_gtt_stolen_entries();
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if (intel_private.base.gtt_stolen_entries == 0) {
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iounmap(intel_private.registers);
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+ iounmap(intel_private.gtt);
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return -ENOMEM;
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}
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@@ -883,7 +901,6 @@ static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
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int page_order, ret;
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struct aper_size_info_fixed *size;
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int num_entries;
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- int gtt_map_size;
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u32 temp;
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size = agp_bridge->current_size;
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@@ -898,17 +915,8 @@ static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
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if (!intel_private.registers)
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return -ENOMEM;
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- intel_private.base.gtt_total_entries = intel_gtt_total_entries();
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- gtt_map_size = intel_private.base.gtt_total_entries * 4;
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-
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- intel_private.gtt = ioremap(temp + I810_PTE_BASE, gtt_map_size);
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- if (!intel_private.gtt) {
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- iounmap(intel_private.registers);
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- return -ENOMEM;
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- }
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-
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+ intel_private.gtt_bus_addr = temp + I810_PTE_BASE;
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temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
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- global_cache_flush(); /* FIXME: ?? */
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ret = intel_gtt_init();
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if (ret != 0)
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@@ -1278,7 +1286,6 @@ static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
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struct aper_size_info_fixed *size;
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int num_entries;
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u32 temp, temp2;
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- int gtt_map_size;
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size = agp_bridge->current_size;
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page_order = size->page_order;
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@@ -1294,23 +1301,12 @@ static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
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if (!intel_private.registers)
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return -ENOMEM;
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- intel_private.base.gtt_total_entries = intel_gtt_total_entries();
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- gtt_map_size = intel_private.base.gtt_total_entries * 4;
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-
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- intel_private.gtt = ioremap(temp2, gtt_map_size);
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- if (!intel_private.gtt) {
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- iounmap(intel_private.registers);
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- return -ENOMEM;
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- }
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-
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+ intel_private.gtt_bus_addr = temp2;
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temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
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- global_cache_flush(); /* FIXME: ? */
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ret = intel_gtt_init();
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- if (ret != 0) {
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- iounmap(intel_private.gtt);
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+ if (ret != 0)
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return ret;
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- }
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agp_bridge->gatt_table = NULL;
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@@ -1348,7 +1344,7 @@ static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge,
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return addr | bridge->driver->masks[type].mask;
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}
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-static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
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+static void intel_i965_get_gtt_range(int *gtt_offset)
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{
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switch (INTEL_GTT_GEN) {
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case 5:
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@@ -1360,8 +1356,6 @@ static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
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*gtt_offset = KB(512);
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break;
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}
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-
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- *gtt_size = intel_private.base.gtt_total_entries * 4;
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}
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/* The intel i965 automatically initializes the agp aperture during POST.
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@@ -1373,7 +1367,7 @@ static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
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struct aper_size_info_fixed *size;
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int num_entries;
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u32 temp;
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- int gtt_offset, gtt_size;
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+ int gtt_offset;
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size = agp_bridge->current_size;
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page_order = size->page_order;
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@@ -1388,25 +1382,13 @@ static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
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if (!intel_private.registers)
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return -ENOMEM;
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- intel_private.base.gtt_total_entries = intel_gtt_total_entries();
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-
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- intel_i965_get_gtt_range(>t_offset, >t_size);
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-
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- intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
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-
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- if (!intel_private.gtt) {
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- iounmap(intel_private.gtt);
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- return -ENOMEM;
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- }
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-
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+ intel_i965_get_gtt_range(>t_offset);
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+ intel_private.gtt_bus_addr = temp + gtt_offset;
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temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
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- global_cache_flush(); /* FIXME: ? */
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ret = intel_gtt_init();
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- if (ret != 0) {
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- iounmap(intel_private.gtt);
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+ if (ret != 0)
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return ret;
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- }
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agp_bridge->gatt_table = NULL;
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