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@@ -58,17 +58,14 @@ extern phys_addr_t lowmem_end_addr;
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* architectures. -- Dan
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*/
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#if defined(CONFIG_8xx)
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-#define flush_HPTE(X, va, pg) _tlbie(va, 0 /* 8xx doesn't care about PID */)
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#define MMU_init_hw() do { } while(0)
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#define mmu_mapin_ram() (0UL)
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#elif defined(CONFIG_4xx)
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-#define flush_HPTE(pid, va, pg) _tlbie(va, pid)
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extern void MMU_init_hw(void);
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extern unsigned long mmu_mapin_ram(void);
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#elif defined(CONFIG_FSL_BOOKE)
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-#define flush_HPTE(pid, va, pg) _tlbie(va, pid)
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extern void MMU_init_hw(void);
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extern unsigned long mmu_mapin_ram(void);
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extern void adjust_total_lowmem(void);
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@@ -77,18 +74,4 @@ extern void adjust_total_lowmem(void);
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/* anything 32-bit except 4xx or 8xx */
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extern void MMU_init_hw(void);
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extern unsigned long mmu_mapin_ram(void);
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-
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-/* Be careful....this needs to be updated if we ever encounter 603 SMPs,
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- * which includes all new 82xx processors. We need tlbie/tlbsync here
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- * in that case (I think). -- Dan.
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- */
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-static inline void flush_HPTE(unsigned context, unsigned long va,
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- unsigned long pdval)
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-{
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- if ((Hash != 0) &&
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- cpu_has_feature(CPU_FTR_HPTE_TABLE))
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- flush_hash_pages(0, va, pdval, 1);
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- else
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- _tlbie(va);
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-}
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#endif
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