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@@ -204,4 +204,23 @@ extern const di_fcn_t dma64proc;
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extern uint dma_addrwidth(si_t *sih, void *dmaregs);
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void dma_walk_packets(struct hnddma_pub *dmah, void (*callback_fnc)
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(void *pkt, void *arg_a), void *arg_a);
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+
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+/*
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+ * DMA(Bug) on some chips seems to declare that the packet is ready, but the
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+ * packet length is not updated yet (by DMA) on the expected time.
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+ * Workaround is to hold processor till DMA updates the length, and stay off
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+ * the bus to allow DMA update the length in buffer
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+ */
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+static inline void dma_spin_for_len(uint len, struct sk_buff *head)
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+{
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+#if defined(__mips__)
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+ if (!len) {
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+ while (!(len = *(u16 *) KSEG1ADDR(head->data)))
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+ udelay(1);
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+
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+ *(u16 *) (head->data) = cpu_to_le16((u16) len);
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+ }
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+#endif /* defined(__mips__) */
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+}
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+
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#endif /* _hnddma_h_ */
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