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@@ -1466,6 +1466,20 @@ static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
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POSTING_READ(DPLL(pipe));
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}
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+static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
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+{
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+ u32 val = 0;
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+
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+ /* Make sure the pipe isn't still relying on us */
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+ assert_pipe_disabled(dev_priv, pipe);
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+
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+ /* Leave integrated clock source enabled */
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+ if (pipe == PIPE_B)
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+ val = DPLL_INTEGRATED_CRI_CLK_VLV;
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+ I915_WRITE(DPLL(pipe), val);
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+ POSTING_READ(DPLL(pipe));
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+}
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+
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void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
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{
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u32 port_mask;
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@@ -3875,7 +3889,9 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
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if (encoder->post_disable)
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encoder->post_disable(encoder);
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- if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
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+ if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
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+ vlv_disable_pll(dev_priv, pipe);
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+ else if (!IS_VALLEYVIEW(dev))
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i9xx_disable_pll(dev_priv, pipe);
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intel_crtc->active = false;
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@@ -4615,9 +4631,9 @@ static void vlv_update_pll(struct intel_crtc *crtc)
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/* Enable DPIO clock input */
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dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
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DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
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- if (pipe)
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+ /* We should never disable this, set it here for state tracking */
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+ if (pipe == PIPE_B)
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dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
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-
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dpll |= DPLL_VCO_ENABLE;
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crtc->config.dpll_hw_state.dpll = dpll;
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@@ -10279,10 +10295,17 @@ void i915_disable_vga_mem(struct drm_device *dev)
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void intel_modeset_init_hw(struct drm_device *dev)
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{
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+ struct drm_i915_private *dev_priv = dev->dev_private;
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+
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intel_prepare_ddi(dev);
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intel_init_clock_gating(dev);
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+ /* Enable the CRI clock source so we can get at the display */
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+ if (IS_VALLEYVIEW(dev))
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+ I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
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+ DPLL_INTEGRATED_CRI_CLK_VLV);
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+
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mutex_lock(&dev->struct_mutex);
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intel_enable_gt_powersave(dev);
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mutex_unlock(&dev->struct_mutex);
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