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@@ -66,15 +66,19 @@
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#define OMAP2_L3_IO_OFFSET 0x90000000
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#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
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+
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+#define OMAP2_L4_IO_OFFSET 0xb2000000
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+#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
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+
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#define OMAP4_L3_IO_OFFSET 0xb4000000
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#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
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+#define OMAP4_L3_PER_IO_OFFSET 0xb1100000
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+#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
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+
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#define OMAP4_GPMC_IO_OFFSET 0xa9000000
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#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
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-#define OMAP2_L4_IO_OFFSET 0xb2000000
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-#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
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-
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#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
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#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
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@@ -214,6 +218,11 @@
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#define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
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#define L4_PER_44XX_SIZE SZ_4M
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+#define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE
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+ /* 0x49000000 --> 0xfb000000 */
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+#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
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+#define L4_ABE_44XX_SIZE SZ_1M
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+
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#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE
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/* 0x54000000 --> 0xfe800000 */
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#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
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@@ -225,6 +234,20 @@
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#define OMAP44XX_GPMC_SIZE SZ_1M
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+#define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE
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+ /* 0x4c000000 --> 0xfd100000 */
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+#define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
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+#define OMAP44XX_EMIF1_SIZE SZ_1M
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+
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+#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
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+ /* 0x4d000000 --> 0xfd200000 */
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+#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
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+#define OMAP44XX_EMIF2_SIZE SZ_1M
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+
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+#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
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+ /* 0x4e000000 --> 0xfd300000 */
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+#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
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+#define OMAP44XX_DMM_SIZE SZ_1M
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/*
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* ----------------------------------------------------------------------------
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* Omap specific register access
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