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@@ -1019,7 +1019,7 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
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/*
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* Retrieve current video scanout position of crtc on a given gpu.
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*
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- * \param rdev Device to query.
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+ * \param dev Device to query.
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* \param crtc Crtc to query.
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* \param *vpos Location where vertical scanout position should be stored.
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* \param *hpos Location where horizontal scanout position should go.
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@@ -1031,72 +1031,74 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
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*
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* \return Flags, or'ed together as follows:
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*
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- * RADEON_SCANOUTPOS_VALID = Query successfull.
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- * RADEON_SCANOUTPOS_INVBL = Inside vblank.
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- * RADEON_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
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+ * DRM_SCANOUTPOS_VALID = Query successfull.
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+ * DRM_SCANOUTPOS_INVBL = Inside vblank.
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+ * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
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* this flag means that returned position may be offset by a constant but
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* unknown small number of scanlines wrt. real scanout position.
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*
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*/
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-int radeon_get_crtc_scanoutpos(struct radeon_device *rdev, int crtc, int *vpos, int *hpos)
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+int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)
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{
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u32 stat_crtc = 0, vbl = 0, position = 0;
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int vbl_start, vbl_end, vtotal, ret = 0;
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bool in_vbl = true;
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+ struct radeon_device *rdev = dev->dev_private;
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+
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if (ASIC_IS_DCE4(rdev)) {
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if (crtc == 0) {
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vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
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EVERGREEN_CRTC0_REGISTER_OFFSET);
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position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
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EVERGREEN_CRTC0_REGISTER_OFFSET);
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- ret |= RADEON_SCANOUTPOS_VALID;
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+ ret |= DRM_SCANOUTPOS_VALID;
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}
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if (crtc == 1) {
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vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
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EVERGREEN_CRTC1_REGISTER_OFFSET);
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position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
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EVERGREEN_CRTC1_REGISTER_OFFSET);
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- ret |= RADEON_SCANOUTPOS_VALID;
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+ ret |= DRM_SCANOUTPOS_VALID;
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}
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if (crtc == 2) {
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vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
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EVERGREEN_CRTC2_REGISTER_OFFSET);
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position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
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EVERGREEN_CRTC2_REGISTER_OFFSET);
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- ret |= RADEON_SCANOUTPOS_VALID;
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+ ret |= DRM_SCANOUTPOS_VALID;
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}
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if (crtc == 3) {
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vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
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EVERGREEN_CRTC3_REGISTER_OFFSET);
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position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
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EVERGREEN_CRTC3_REGISTER_OFFSET);
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- ret |= RADEON_SCANOUTPOS_VALID;
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+ ret |= DRM_SCANOUTPOS_VALID;
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}
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if (crtc == 4) {
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vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
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EVERGREEN_CRTC4_REGISTER_OFFSET);
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position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
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EVERGREEN_CRTC4_REGISTER_OFFSET);
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- ret |= RADEON_SCANOUTPOS_VALID;
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+ ret |= DRM_SCANOUTPOS_VALID;
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}
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if (crtc == 5) {
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vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
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EVERGREEN_CRTC5_REGISTER_OFFSET);
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position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
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EVERGREEN_CRTC5_REGISTER_OFFSET);
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- ret |= RADEON_SCANOUTPOS_VALID;
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+ ret |= DRM_SCANOUTPOS_VALID;
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}
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} else if (ASIC_IS_AVIVO(rdev)) {
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if (crtc == 0) {
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vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
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position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
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- ret |= RADEON_SCANOUTPOS_VALID;
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+ ret |= DRM_SCANOUTPOS_VALID;
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}
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if (crtc == 1) {
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vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
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position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
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- ret |= RADEON_SCANOUTPOS_VALID;
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+ ret |= DRM_SCANOUTPOS_VALID;
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}
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} else {
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/* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
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@@ -1112,7 +1114,7 @@ int radeon_get_crtc_scanoutpos(struct radeon_device *rdev, int crtc, int *vpos,
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if (!(stat_crtc & 1))
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in_vbl = false;
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- ret |= RADEON_SCANOUTPOS_VALID;
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+ ret |= DRM_SCANOUTPOS_VALID;
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}
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if (crtc == 1) {
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vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
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@@ -1122,7 +1124,7 @@ int radeon_get_crtc_scanoutpos(struct radeon_device *rdev, int crtc, int *vpos,
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if (!(stat_crtc & 1))
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in_vbl = false;
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- ret |= RADEON_SCANOUTPOS_VALID;
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+ ret |= DRM_SCANOUTPOS_VALID;
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}
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}
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@@ -1133,13 +1135,13 @@ int radeon_get_crtc_scanoutpos(struct radeon_device *rdev, int crtc, int *vpos,
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/* Valid vblank area boundaries from gpu retrieved? */
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if (vbl > 0) {
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/* Yes: Decode. */
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- ret |= RADEON_SCANOUTPOS_ACCURATE;
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+ ret |= DRM_SCANOUTPOS_ACCURATE;
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vbl_start = vbl & 0x1fff;
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vbl_end = (vbl >> 16) & 0x1fff;
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}
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else {
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/* No: Fake something reasonable which gives at least ok results. */
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- vbl_start = rdev->mode_info.crtcs[crtc]->base.mode.crtc_vdisplay;
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+ vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
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vbl_end = 0;
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}
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@@ -1155,7 +1157,7 @@ int radeon_get_crtc_scanoutpos(struct radeon_device *rdev, int crtc, int *vpos,
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/* Inside "upper part" of vblank area? Apply corrective offset if so: */
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if (in_vbl && (*vpos >= vbl_start)) {
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- vtotal = rdev->mode_info.crtcs[crtc]->base.mode.crtc_vtotal;
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+ vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
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*vpos = *vpos - vtotal;
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}
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@@ -1164,7 +1166,7 @@ int radeon_get_crtc_scanoutpos(struct radeon_device *rdev, int crtc, int *vpos,
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/* In vblank? */
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if (in_vbl)
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- ret |= RADEON_SCANOUTPOS_INVBL;
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+ ret |= DRM_SCANOUTPOS_INVBL;
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return ret;
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}
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