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atl1c: enlarge L1 response waiting timer

The hardware incorrectly process L0S/L1 entrance if the chipset/root
response after specific/shorter timer and cause system hang.
Enlarge the timeout value to avoid this issue.

Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Huang, Xiong 13 years ago
parent
229e6b6e9c
commit
f56fa56737
1 changed files with 1 additions and 1 deletions
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  1. 1 1
      drivers/net/ethernet/atheros/atl1c/atl1c_hw.h

+ 1 - 1
drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
View File 

@@ -157,7 +157,7 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
 
 #define PM_CTRL_PM_REQ_TIMER_MASK	0xFUL
 
 #define PM_CTRL_PM_REQ_TIMER_MASK	0xFUL
 
 #define PM_CTRL_PM_REQ_TIMER_SHIFT	20	/* pm_request_l1 time > @
 
 #define PM_CTRL_PM_REQ_TIMER_SHIFT	20	/* pm_request_l1 time > @
 
 						 * ->L0s not L1 */
 
 						 * ->L0s not L1 */
 
-#define PM_CTRL_PM_REQ_TO_DEF		0xC
 
+#define PM_CTRL_PM_REQ_TO_DEF		0xF
 
 #define PMCTRL_TXL1_AFTER_L0S		BIT(19)	/* l1dv2.0+ */
 
 #define PMCTRL_TXL1_AFTER_L0S		BIT(19)	/* l1dv2.0+ */
 
 #define L1D_PMCTRL_L1_ENTRY_TM_MASK	7UL	/* l1dv2.0+, 3bits */
 
 #define L1D_PMCTRL_L1_ENTRY_TM_MASK	7UL	/* l1dv2.0+, 3bits */
 
 #define L1D_PMCTRL_L1_ENTRY_TM_SHIFT	16
 
 #define L1D_PMCTRL_L1_ENTRY_TM_SHIFT	16