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@@ -5457,7 +5457,8 @@ static int bnx2x_init_hw_func(struct bnx2x *bp)
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struct bnx2x_ilt *ilt = BP_ILT(bp);
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struct bnx2x_ilt *ilt = BP_ILT(bp);
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u16 cdu_ilt_start;
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u16 cdu_ilt_start;
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u32 addr, val;
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u32 addr, val;
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- int i;
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+ u32 main_mem_base, main_mem_size, main_mem_prty_clr;
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+ int i, main_mem_width;
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DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
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DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
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@@ -5706,6 +5707,31 @@ static int bnx2x_init_hw_func(struct bnx2x *bp)
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bnx2x_init_block(bp, MCP_BLOCK, FUNC0_STAGE + func);
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bnx2x_init_block(bp, MCP_BLOCK, FUNC0_STAGE + func);
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bnx2x_init_block(bp, DMAE_BLOCK, FUNC0_STAGE + func);
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bnx2x_init_block(bp, DMAE_BLOCK, FUNC0_STAGE + func);
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+ if (CHIP_IS_E1x(bp)) {
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+ main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
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+ main_mem_base = HC_REG_MAIN_MEMORY +
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+ BP_PORT(bp) * (main_mem_size * 4);
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+ main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
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+ main_mem_width = 8;
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+
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+ val = REG_RD(bp, main_mem_prty_clr);
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+ if (val)
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+ DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
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+ "block during "
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+ "function init (0x%x)!\n", val);
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+
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+ /* Clear "false" parity errors in MSI-X table */
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+ for (i = main_mem_base;
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+ i < main_mem_base + main_mem_size * 4;
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+ i += main_mem_width) {
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+ bnx2x_read_dmae(bp, i, main_mem_width / 4);
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+ bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
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+ i, main_mem_width / 4);
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+ }
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+ /* Clear HC parity attention */
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+ REG_RD(bp, main_mem_prty_clr);
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+ }
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+
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bnx2x_phy_probe(&bp->link_params);
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bnx2x_phy_probe(&bp->link_params);
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return 0;
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return 0;
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