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@@ -37,8 +37,6 @@
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#define SMC_RAM_END 0x20000
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-#define DDR3_DRAM_ROWS 0x2000
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-
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#define SCLK_MIN_DEEPSLEEP_FREQ 1350
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static const struct si_cac_config_reg cac_weights_tahiti[] =
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@@ -4040,16 +4038,15 @@ static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
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static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
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u32 engine_clock)
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{
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- struct rv7xx_power_info *pi = rv770_get_pi(rdev);
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u32 dram_rows;
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u32 dram_refresh_rate;
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u32 mc_arb_rfsh_rate;
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u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
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- if (pi->mem_gddr5)
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- dram_rows = 1 << (tmp + 10);
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+ if (tmp >= 4)
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+ dram_rows = 16384;
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else
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- dram_rows = DDR3_DRAM_ROWS;
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+ dram_rows = 1 << (tmp + 10);
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dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
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mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
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