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drm/i915: Capture ERROR register on Sandybridge hangs

This holds error state from the main graphics arbiter mainly involving
the DMA engine and address translation.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Chris Wilson 14 년 전
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4개의 변경된 파일17개의 추가작업 그리고 7개의 파일을 삭제
  1. 3 0
      drivers/gpu/drm/i915/i915_debugfs.c
  2. 1 0
      drivers/gpu/drm/i915/i915_drv.h
  3. 11 7
      drivers/gpu/drm/i915/i915_irq.c
  4. 2 0
      drivers/gpu/drm/i915/i915_reg.h

+ 3 - 0
drivers/gpu/drm/i915/i915_debugfs.c

@@ -615,6 +615,9 @@ static int i915_error_state(struct seq_file *m, void *unused)
 	seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
 		   error->time.tv_usec);
 	seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
+	if (INTEL_INFO(dev)->gen >= 6) {
+		seq_printf(m, "ERROR: 0x%08x\n", error->error);
+	}
 	seq_printf(m, "EIR: 0x%08x\n", error->eir);
 	seq_printf(m, "  PGTBL_ER: 0x%08x\n", error->pgtbl_er);
 	seq_printf(m, "  INSTPM: 0x%08x\n", error->instpm);

+ 1 - 0
drivers/gpu/drm/i915/i915_drv.h

@@ -142,6 +142,7 @@ struct sdvo_device_mapping {
 struct drm_i915_error_state {
 	u32 eir;
 	u32 pgtbl_er;
+	u32 error; /* gen6+ */
 	u32 pipeastat;
 	u32 pipebstat;
 	u32 ipeir;

+ 11 - 7
drivers/gpu/drm/i915/i915_irq.c

@@ -592,13 +592,11 @@ static void i915_capture_error_state(struct drm_device *dev)
 	error->pipeastat = I915_READ(PIPEASTAT);
 	error->pipebstat = I915_READ(PIPEBSTAT);
 	error->instpm = I915_READ(INSTPM);
-	if (INTEL_INFO(dev)->gen < 4) {
-		error->ipeir = I915_READ(IPEIR);
-		error->ipehr = I915_READ(IPEHR);
-		error->instdone = I915_READ(INSTDONE);
-		error->acthd = I915_READ(ACTHD);
-		error->bbaddr = 0;
-	} else {
+	error->error = 0;
+	if (INTEL_INFO(dev)->gen >= 6) {
+		error->error = I915_READ(ERROR_GEN6);
+	}
+	if (INTEL_INFO(dev)->gen >= 4) {
 		error->ipeir = I915_READ(IPEIR_I965);
 		error->ipehr = I915_READ(IPEHR_I965);
 		error->instdone = I915_READ(INSTDONE_I965);
@@ -606,6 +604,12 @@ static void i915_capture_error_state(struct drm_device *dev)
 		error->instdone1 = I915_READ(INSTDONE1);
 		error->acthd = I915_READ(ACTHD_I965);
 		error->bbaddr = I915_READ64(BB_ADDR);
+	} else {
+		error->ipeir = I915_READ(IPEIR);
+		error->ipehr = I915_READ(IPEHR);
+		error->instdone = I915_READ(INSTDONE);
+		error->acthd = I915_READ(ACTHD);
+		error->bbaddr = 0;
 	}
 
 	bbaddr = i915_ringbuffer_last_batch(dev);

+ 2 - 0
drivers/gpu/drm/i915/i915_reg.h

@@ -306,6 +306,8 @@
 #define NOPID		0x02094
 #define HWSTAM		0x02098
 
+#define ERROR_GEN6	0x040a0
+
 #define MI_MODE		0x0209c
 # define VS_TIMER_DISPATCH				(1 << 6)
 # define MI_FLUSH_ENABLE				(1 << 11)