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@@ -3243,15 +3243,6 @@ relink:
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pci_write_config_word(tp->pdev,
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tp->pcie_cap + PCI_EXP_LNKCTL,
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newlnkctl);
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- } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
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- u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
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- if (tp->link_config.active_speed == SPEED_100 ||
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- tp->link_config.active_speed == SPEED_10)
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- newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
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- else
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- newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
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- if (newreg != oldreg)
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- tw32(TG3_PCIE_LNKCTL, newreg);
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}
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if (current_link_up != netif_carrier_ok(tp->dev)) {
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@@ -7180,15 +7171,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
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tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
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- }
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- if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
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- val = tr32(TG3_PCIE_LNKCTL);
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- if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
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- val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
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- else
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- val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
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- tw32(TG3_PCIE_LNKCTL, val);
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+ val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
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+ tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
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}
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/* This works around an issue with Athlon chipsets on
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@@ -12951,11 +12936,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
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tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
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- if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
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- tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
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- tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
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- tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
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-
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err = tg3_mdio_init(tp);
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if (err)
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return err;
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