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@@ -633,8 +633,7 @@ int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter,
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struct hwtstamp_config config;
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u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED;
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u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED;
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- u32 tsync_rx_mtrl = 0;
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- bool is_l4 = false;
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+ u32 tsync_rx_mtrl = PTP_EV_PORT << 16;
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bool is_l2 = false;
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u32 regval;
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@@ -657,16 +656,15 @@ int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter,
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switch (config.rx_filter) {
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case HWTSTAMP_FILTER_NONE:
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tsync_rx_ctl = 0;
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+ tsync_rx_mtrl = 0;
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break;
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case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
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tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
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tsync_rx_mtrl = IXGBE_RXMTRL_V1_SYNC_MSG;
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- is_l4 = true;
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break;
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case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
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tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
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tsync_rx_mtrl = IXGBE_RXMTRL_V1_DELAY_REQ_MSG;
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- is_l4 = true;
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break;
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case HWTSTAMP_FILTER_PTP_V2_EVENT:
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case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
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@@ -679,7 +677,6 @@ int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter,
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case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
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tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2;
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is_l2 = true;
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- is_l4 = true;
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config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
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break;
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case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
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@@ -713,33 +710,6 @@ int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter,
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else
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IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
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-#define PTP_PORT 319
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- /* L4 Queue Filter[3]: filter by destination port and protocol */
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- if (is_l4) {
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- u32 ftqf = (IXGBE_FTQF_PROTOCOL_UDP /* UDP */
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- | IXGBE_FTQF_POOL_MASK_EN /* Pool not compared */
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- | IXGBE_FTQF_QUEUE_ENABLE);
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-
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- ftqf |= ((IXGBE_FTQF_PROTOCOL_COMP_MASK /* protocol check */
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- & IXGBE_FTQF_DEST_PORT_MASK /* dest check */
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- & IXGBE_FTQF_SOURCE_PORT_MASK) /* source check */
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- << IXGBE_FTQF_5TUPLE_MASK_SHIFT);
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-
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- IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(3),
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- (3 << IXGBE_IMIR_RX_QUEUE_SHIFT_82599 |
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- IXGBE_IMIR_SIZE_BP_82599));
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-
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- /* enable port check */
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- IXGBE_WRITE_REG(hw, IXGBE_SDPQF(3),
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- (htons(PTP_PORT) |
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- htons(PTP_PORT) << 16));
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-
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- IXGBE_WRITE_REG(hw, IXGBE_FTQF(3), ftqf);
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-
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- tsync_rx_mtrl |= PTP_PORT << 16;
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- } else {
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- IXGBE_WRITE_REG(hw, IXGBE_FTQF(3), 0);
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- }
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/* enable/disable TX */
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regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
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