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@@ -5167,41 +5167,9 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
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BUG_ON(val != final);
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}
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-/*
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- * Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O.
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- * WaMPhyProgramming:hsw
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- */
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-static void lpt_init_pch_refclk(struct drm_device *dev)
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+static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
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{
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- struct drm_i915_private *dev_priv = dev->dev_private;
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- struct drm_mode_config *mode_config = &dev->mode_config;
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- struct intel_encoder *encoder;
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- bool has_vga = false;
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- u32 tmp;
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-
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- list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
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- switch (encoder->type) {
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- case INTEL_OUTPUT_ANALOG:
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- has_vga = true;
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- break;
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- }
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- }
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-
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- if (!has_vga)
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- return;
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-
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- mutex_lock(&dev_priv->dpio_lock);
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-
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- tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
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- tmp &= ~SBI_SSCCTL_DISABLE;
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- tmp |= SBI_SSCCTL_PATHALT;
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- intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
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-
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- udelay(24);
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-
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- tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
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- tmp &= ~SBI_SSCCTL_PATHALT;
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- intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
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+ uint32_t tmp;
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tmp = I915_READ(SOUTH_CHICKEN2);
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tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
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@@ -5218,6 +5186,12 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
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if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
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FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
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DRM_ERROR("FDI mPHY reset de-assert timeout\n");
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+}
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+
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+/* WaMPhyProgramming:hsw */
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+static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
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+{
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+ uint32_t tmp;
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tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
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tmp &= ~(0xFF << 24);
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@@ -5287,6 +5261,43 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
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tmp &= ~(0xF << 28);
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tmp |= (4 << 28);
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intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
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+}
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+
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+/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
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+static void lpt_init_pch_refclk(struct drm_device *dev)
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+{
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+ struct drm_i915_private *dev_priv = dev->dev_private;
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+ struct drm_mode_config *mode_config = &dev->mode_config;
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+ struct intel_encoder *encoder;
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+ bool has_vga = false;
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+ u32 tmp;
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+
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+ list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
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+ switch (encoder->type) {
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+ case INTEL_OUTPUT_ANALOG:
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+ has_vga = true;
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+ break;
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+ }
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+ }
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+
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+ if (!has_vga)
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+ return;
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+
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+ mutex_lock(&dev_priv->dpio_lock);
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+
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+ tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
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+ tmp &= ~SBI_SSCCTL_DISABLE;
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+ tmp |= SBI_SSCCTL_PATHALT;
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+ intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
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+
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+ udelay(24);
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+
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+ tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
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+ tmp &= ~SBI_SSCCTL_PATHALT;
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+ intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
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+
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+ lpt_reset_fdi_mphy(dev_priv);
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+ lpt_program_fdi_mphy(dev_priv);
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/* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
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tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
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