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@@ -35,7 +35,7 @@
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#ifdef CONFIG_FSL_BOOKE
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#define WDT_PERIOD_DEFAULT 63 /* Ex. wdt_period=28 bus=333Mhz , reset=~40sec */
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#else
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-#define WDT_PERIOD_DEFAULT 4 /* Refer to the PPC40x and PPC4xx manuals */
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+#define WDT_PERIOD_DEFAULT 3 /* Refer to the PPC40x and PPC4xx manuals */
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#endif /* for timing information */
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u32 booke_wdt_enabled = 0;
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@@ -47,6 +47,14 @@ u32 booke_wdt_period = WDT_PERIOD_DEFAULT;
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#define WDTP(x) (TCR_WP(x))
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#endif
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+/*
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+ * booke_wdt_ping:
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+ */
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+static __inline__ void booke_wdt_ping(void)
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+{
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+ mtspr(SPRN_TSR, TSR_ENW|TSR_WIS);
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+}
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+
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/*
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* booke_wdt_enable:
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*/
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@@ -54,20 +62,14 @@ static __inline__ void booke_wdt_enable(void)
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{
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u32 val;
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+ /* clear status before enabling watchdog */
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+ booke_wdt_ping();
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val = mfspr(SPRN_TCR);
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val |= (TCR_WIE|TCR_WRC(WRC_CHIP)|WDTP(booke_wdt_period));
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mtspr(SPRN_TCR, val);
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}
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-/*
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- * booke_wdt_ping:
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- */
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-static __inline__ void booke_wdt_ping(void)
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-{
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- mtspr(SPRN_TSR, TSR_ENW|TSR_WIS);
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-}
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-
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/*
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* booke_wdt_write:
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*/
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