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@@ -39,7 +39,12 @@
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#define PSC0_BASE_ADDR 0xb1a00000
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#define PSC1_BASE_ADDR 0xb1b00000
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#define PSC2_BASE_ADDR 0xb0a00000
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-#define PSC3_BASE_ADDR 0xb0d00000
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+#define PSC3_BASE_ADDR 0xb0b00000
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+#endif
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+
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+#ifdef CONFIG_SOC_AU1200
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+#define PSC0_BASE_ADDR 0xb1a00000
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+#define PSC1_BASE_ADDR 0xb1b00000
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#endif
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/* The PSC select and control registers are common to
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@@ -227,6 +232,8 @@ typedef struct psc_i2s {
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#define PSC_I2SCFG_DD_DISABLE (1 << 27)
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#define PSC_I2SCFG_DE_ENABLE (1 << 26)
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#define PSC_I2SCFG_SET_WS(x) (((((x) / 2) - 1) & 0x7f) << 16)
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+#define PSC_I2SCFG_WS(n) ((n & 0xFF) << 16)
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+#define PSC_I2SCFG_WS_MASK (PSC_I2SCFG_WS(0x3F))
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#define PSC_I2SCFG_WI (1 << 15)
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#define PSC_I2SCFG_DIV_MASK (3 << 13)
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