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@@ -1008,6 +1008,97 @@ void __init dm365_init(void)
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davinci_common_init(&davinci_soc_info_dm365);
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}
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+static struct resource dm365_vpss_resources[] = {
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+ {
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+ /* VPSS ISP5 Base address */
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+ .name = "isp5",
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+ .start = 0x01c70000,
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+ .end = 0x01c70000 + 0xff,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ /* VPSS CLK Base address */
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+ .name = "vpss",
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+ .start = 0x01c70200,
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+ .end = 0x01c70200 + 0xff,
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+ .flags = IORESOURCE_MEM,
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+ },
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+};
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+
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+static struct platform_device dm365_vpss_device = {
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+ .name = "vpss",
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+ .id = -1,
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+ .dev.platform_data = "dm365_vpss",
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+ .num_resources = ARRAY_SIZE(dm365_vpss_resources),
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+ .resource = dm365_vpss_resources,
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+};
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+
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+static struct resource vpfe_resources[] = {
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+ {
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+ .start = IRQ_VDINT0,
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+ .end = IRQ_VDINT0,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+ {
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+ .start = IRQ_VDINT1,
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+ .end = IRQ_VDINT1,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
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+static struct platform_device vpfe_capture_dev = {
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+ .name = CAPTURE_DRV_NAME,
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+ .id = -1,
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+ .num_resources = ARRAY_SIZE(vpfe_resources),
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+ .resource = vpfe_resources,
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+ .dev = {
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+ .dma_mask = &vpfe_capture_dma_mask,
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+ .coherent_dma_mask = DMA_BIT_MASK(32),
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+ },
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+};
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+
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+static void dm365_isif_setup_pinmux(void)
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+{
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+ davinci_cfg_reg(DM365_VIN_CAM_WEN);
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+ davinci_cfg_reg(DM365_VIN_CAM_VD);
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+ davinci_cfg_reg(DM365_VIN_CAM_HD);
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+ davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
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+ davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
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+}
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+
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+static struct resource isif_resource[] = {
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+ /* ISIF Base address */
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+ {
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+ .start = 0x01c71000,
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+ .end = 0x01c71000 + 0x1ff,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ /* ISIF Linearization table 0 */
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+ {
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+ .start = 0x1C7C000,
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+ .end = 0x1C7C000 + 0x2ff,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ /* ISIF Linearization table 1 */
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+ {
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+ .start = 0x1C7C400,
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+ .end = 0x1C7C400 + 0x2ff,
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+ .flags = IORESOURCE_MEM,
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+ },
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+};
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+static struct platform_device dm365_isif_dev = {
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+ .name = "isif",
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+ .id = -1,
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+ .num_resources = ARRAY_SIZE(isif_resource),
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+ .resource = isif_resource,
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+ .dev = {
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+ .dma_mask = &vpfe_capture_dma_mask,
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+ .coherent_dma_mask = DMA_BIT_MASK(32),
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+ .platform_data = dm365_isif_setup_pinmux,
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+ },
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+};
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+
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static int __init dm365_init_devices(void)
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{
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if (!cpu_is_davinci_dm365())
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@@ -1016,7 +1107,16 @@ static int __init dm365_init_devices(void)
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davinci_cfg_reg(DM365_INT_EDMA_CC);
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platform_device_register(&dm365_edma_device);
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platform_device_register(&dm365_emac_device);
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-
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+ /* Add isif clock alias */
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+ clk_add_alias("master", dm365_isif_dev.name, "vpss_master", NULL);
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+ platform_device_register(&dm365_vpss_device);
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+ platform_device_register(&dm365_isif_dev);
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+ platform_device_register(&vpfe_capture_dev);
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return 0;
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}
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postcore_initcall(dm365_init_devices);
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+
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+void dm365_set_vpfe_config(struct vpfe_config *cfg)
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+{
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+ vpfe_capture_dev.dev.platform_data = cfg;
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+}
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