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@@ -144,7 +144,7 @@ struct tmds_config {
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u32 drive_current;
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};
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-static const struct tmds_config tegra2_tmds_config[] = {
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+static const struct tmds_config tegra20_tmds_config[] = {
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{ /* slow pixel clock modes */
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.pclk = 27000000,
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.pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
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@@ -177,7 +177,7 @@ static const struct tmds_config tegra2_tmds_config[] = {
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},
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};
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-static const struct tmds_config tegra3_tmds_config[] = {
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+static const struct tmds_config tegra30_tmds_config[] = {
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{ /* 480p modes */
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.pclk = 27000000,
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.pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
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@@ -704,11 +704,11 @@ static int tegra_output_hdmi_enable(struct tegra_output *output)
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/* TMDS CONFIG */
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if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
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- num_tmds = ARRAY_SIZE(tegra3_tmds_config);
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- tmds = tegra3_tmds_config;
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+ num_tmds = ARRAY_SIZE(tegra30_tmds_config);
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+ tmds = tegra30_tmds_config;
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} else {
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- num_tmds = ARRAY_SIZE(tegra2_tmds_config);
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- tmds = tegra2_tmds_config;
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+ num_tmds = ARRAY_SIZE(tegra20_tmds_config);
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+ tmds = tegra20_tmds_config;
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}
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for (i = 0; i < num_tmds; i++) {
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