|
@@ -0,0 +1,67 @@
|
|
|
|
+/*
|
|
|
|
+ * Device Tree Source for OMAP2 SoC
|
|
|
|
+ *
|
|
|
|
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
|
|
|
+ *
|
|
|
|
+ * This file is licensed under the terms of the GNU General Public License
|
|
|
|
+ * version 2. This program is licensed "as is" without any warranty of any
|
|
|
|
+ * kind, whether express or implied.
|
|
|
|
+ */
|
|
|
|
+
|
|
|
|
+/include/ "skeleton.dtsi"
|
|
|
|
+
|
|
|
|
+/ {
|
|
|
|
+ compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
|
|
|
|
+
|
|
|
|
+ aliases {
|
|
|
|
+ serial0 = &uart1;
|
|
|
|
+ serial1 = &uart2;
|
|
|
|
+ serial2 = &uart3;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ cpus {
|
|
|
|
+ cpu@0 {
|
|
|
|
+ compatible = "arm,arm1136jf-s";
|
|
|
|
+ };
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ soc {
|
|
|
|
+ compatible = "ti,omap-infra";
|
|
|
|
+ mpu {
|
|
|
|
+ compatible = "ti,omap2-mpu";
|
|
|
|
+ ti,hwmods = "mpu";
|
|
|
|
+ };
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ ocp {
|
|
|
|
+ compatible = "simple-bus";
|
|
|
|
+ #address-cells = <1>;
|
|
|
|
+ #size-cells = <1>;
|
|
|
|
+ ranges;
|
|
|
|
+ ti,hwmods = "l3_main";
|
|
|
|
+
|
|
|
|
+ intc: interrupt-controller@1 {
|
|
|
|
+ compatible = "ti,omap2-intc";
|
|
|
|
+ interrupt-controller;
|
|
|
|
+ #interrupt-cells = <1>;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ uart1: serial@4806a000 {
|
|
|
|
+ compatible = "ti,omap2-uart";
|
|
|
|
+ ti,hwmods = "uart1";
|
|
|
|
+ clock-frequency = <48000000>;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ uart2: serial@4806c000 {
|
|
|
|
+ compatible = "ti,omap2-uart";
|
|
|
|
+ ti,hwmods = "uart2";
|
|
|
|
+ clock-frequency = <48000000>;
|
|
|
|
+ };
|
|
|
|
+
|
|
|
|
+ uart3: serial@4806e000 {
|
|
|
|
+ compatible = "ti,omap2-uart";
|
|
|
|
+ ti,hwmods = "uart3";
|
|
|
|
+ clock-frequency = <48000000>;
|
|
|
|
+ };
|
|
|
|
+ };
|
|
|
|
+};
|