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@@ -47,6 +47,10 @@ MODULE_ALIAS("platform:pxa2xx-spi");
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#define MAX_BUSES 3
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#define MAX_BUSES 3
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+#define RX_THRESH_DFLT 8
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+#define TX_THRESH_DFLT 8
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+#define TIMOUT_DFLT 1000
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+
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#define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
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#define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
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#define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
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#define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
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#define IS_DMA_ALIGNED(x) ((((u32)(x)) & 0x07) == 0)
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#define IS_DMA_ALIGNED(x) ((((u32)(x)) & 0x07) == 0)
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@@ -1171,6 +1175,8 @@ static int setup(struct spi_device *spi)
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struct driver_data *drv_data = spi_master_get_devdata(spi->master);
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struct driver_data *drv_data = spi_master_get_devdata(spi->master);
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struct ssp_device *ssp = drv_data->ssp;
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struct ssp_device *ssp = drv_data->ssp;
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unsigned int clk_div;
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unsigned int clk_div;
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+ uint tx_thres = TX_THRESH_DFLT;
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+ uint rx_thres = RX_THRESH_DFLT;
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if (!spi->bits_per_word)
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if (!spi->bits_per_word)
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spi->bits_per_word = 8;
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spi->bits_per_word = 8;
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@@ -1209,8 +1215,7 @@ static int setup(struct spi_device *spi)
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chip->cs_control = null_cs_control;
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chip->cs_control = null_cs_control;
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chip->enable_dma = 0;
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chip->enable_dma = 0;
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- chip->timeout = 1000;
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- chip->threshold = SSCR1_RxTresh(1) | SSCR1_TxTresh(1);
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+ chip->timeout = TIMOUT_DFLT;
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chip->dma_burst_size = drv_data->master_info->enable_dma ?
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chip->dma_burst_size = drv_data->master_info->enable_dma ?
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DCMD_BURST8 : 0;
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DCMD_BURST8 : 0;
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}
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}
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@@ -1224,22 +1229,21 @@ static int setup(struct spi_device *spi)
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if (chip_info) {
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if (chip_info) {
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if (chip_info->cs_control)
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if (chip_info->cs_control)
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chip->cs_control = chip_info->cs_control;
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chip->cs_control = chip_info->cs_control;
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-
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- chip->timeout = chip_info->timeout;
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-
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- chip->threshold = (SSCR1_RxTresh(chip_info->rx_threshold) &
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- SSCR1_RFT) |
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- (SSCR1_TxTresh(chip_info->tx_threshold) &
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- SSCR1_TFT);
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-
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- chip->enable_dma = chip_info->dma_burst_size != 0
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- && drv_data->master_info->enable_dma;
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+ if (chip_info->timeout)
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+ chip->timeout = chip_info->timeout;
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+ if (chip_info->tx_threshold)
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+ tx_thres = chip_info->tx_threshold;
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+ if (chip_info->rx_threshold)
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+ rx_thres = chip_info->rx_threshold;
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+ chip->enable_dma = drv_data->master_info->enable_dma;
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chip->dma_threshold = 0;
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chip->dma_threshold = 0;
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-
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if (chip_info->enable_loopback)
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if (chip_info->enable_loopback)
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chip->cr1 = SSCR1_LBM;
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chip->cr1 = SSCR1_LBM;
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}
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}
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+ chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
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+ (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
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+
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/* set dma burst and threshold outside of chip_info path so that if
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/* set dma burst and threshold outside of chip_info path so that if
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* chip_info goes away after setting chip->enable_dma, the
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* chip_info goes away after setting chip->enable_dma, the
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* burst and threshold can still respond to changes in bits_per_word */
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* burst and threshold can still respond to changes in bits_per_word */
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@@ -1268,17 +1272,19 @@ static int setup(struct spi_device *spi)
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/* NOTE: PXA25x_SSP _could_ use external clocking ... */
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/* NOTE: PXA25x_SSP _could_ use external clocking ... */
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if (drv_data->ssp_type != PXA25x_SSP)
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if (drv_data->ssp_type != PXA25x_SSP)
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- dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n",
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+ dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d, %s\n",
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spi->bits_per_word,
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spi->bits_per_word,
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clk_get_rate(ssp->clk)
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clk_get_rate(ssp->clk)
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/ (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
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/ (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
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- spi->mode & 0x3);
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+ spi->mode & 0x3,
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+ chip->enable_dma ? "DMA" : "PIO");
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else
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else
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- dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d\n",
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+ dev_dbg(&spi->dev, "%d bits/word, %ld Hz, mode %d, %s\n",
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spi->bits_per_word,
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spi->bits_per_word,
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- clk_get_rate(ssp->clk)
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+ clk_get_rate(ssp->clk) / 2
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/ (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
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/ (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
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- spi->mode & 0x3);
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+ spi->mode & 0x3,
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+ chip->enable_dma ? "DMA" : "PIO");
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if (spi->bits_per_word <= 8) {
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if (spi->bits_per_word <= 8) {
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chip->n_bytes = 1;
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chip->n_bytes = 1;
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@@ -1498,7 +1504,9 @@ static int __init pxa2xx_spi_probe(struct platform_device *pdev)
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/* Load default SSP configuration */
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/* Load default SSP configuration */
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write_SSCR0(0, drv_data->ioaddr);
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write_SSCR0(0, drv_data->ioaddr);
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- write_SSCR1(SSCR1_RxTresh(4) | SSCR1_TxTresh(12), drv_data->ioaddr);
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+ write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
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+ SSCR1_TxTresh(TX_THRESH_DFLT),
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+ drv_data->ioaddr);
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write_SSCR0(SSCR0_SerClkDiv(2)
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write_SSCR0(SSCR0_SerClkDiv(2)
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| SSCR0_Motorola
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| SSCR0_Motorola
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| SSCR0_DataSize(8),
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| SSCR0_DataSize(8),
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