|
@@ -153,10 +153,11 @@ enum exynos4_gpio_number {
|
|
#define EXYNOS5_GPIO_B2_NR (4)
|
|
#define EXYNOS5_GPIO_B2_NR (4)
|
|
#define EXYNOS5_GPIO_B3_NR (4)
|
|
#define EXYNOS5_GPIO_B3_NR (4)
|
|
#define EXYNOS5_GPIO_C0_NR (7)
|
|
#define EXYNOS5_GPIO_C0_NR (7)
|
|
-#define EXYNOS5_GPIO_C1_NR (7)
|
|
|
|
|
|
+#define EXYNOS5_GPIO_C1_NR (4)
|
|
#define EXYNOS5_GPIO_C2_NR (7)
|
|
#define EXYNOS5_GPIO_C2_NR (7)
|
|
#define EXYNOS5_GPIO_C3_NR (7)
|
|
#define EXYNOS5_GPIO_C3_NR (7)
|
|
-#define EXYNOS5_GPIO_D0_NR (8)
|
|
|
|
|
|
+#define EXYNOS5_GPIO_C4_NR (7)
|
|
|
|
+#define EXYNOS5_GPIO_D0_NR (4)
|
|
#define EXYNOS5_GPIO_D1_NR (8)
|
|
#define EXYNOS5_GPIO_D1_NR (8)
|
|
#define EXYNOS5_GPIO_Y0_NR (6)
|
|
#define EXYNOS5_GPIO_Y0_NR (6)
|
|
#define EXYNOS5_GPIO_Y1_NR (4)
|
|
#define EXYNOS5_GPIO_Y1_NR (4)
|
|
@@ -199,7 +200,8 @@ enum exynos5_gpio_number {
|
|
EXYNOS5_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
|
|
EXYNOS5_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
|
|
EXYNOS5_GPIO_C2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
|
|
EXYNOS5_GPIO_C2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
|
|
EXYNOS5_GPIO_C3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
|
|
EXYNOS5_GPIO_C3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
|
|
- EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
|
|
|
|
|
|
+ EXYNOS5_GPIO_C4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
|
|
|
|
+ EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
|
|
EXYNOS5_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
|
|
EXYNOS5_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
|
|
EXYNOS5_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
|
|
EXYNOS5_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
|
|
EXYNOS5_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
|
|
EXYNOS5_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
|
|
@@ -242,6 +244,7 @@ enum exynos5_gpio_number {
|
|
#define EXYNOS5_GPC1(_nr) (EXYNOS5_GPIO_C1_START + (_nr))
|
|
#define EXYNOS5_GPC1(_nr) (EXYNOS5_GPIO_C1_START + (_nr))
|
|
#define EXYNOS5_GPC2(_nr) (EXYNOS5_GPIO_C2_START + (_nr))
|
|
#define EXYNOS5_GPC2(_nr) (EXYNOS5_GPIO_C2_START + (_nr))
|
|
#define EXYNOS5_GPC3(_nr) (EXYNOS5_GPIO_C3_START + (_nr))
|
|
#define EXYNOS5_GPC3(_nr) (EXYNOS5_GPIO_C3_START + (_nr))
|
|
|
|
+#define EXYNOS5_GPC4(_nr) (EXYNOS5_GPIO_C4_START + (_nr))
|
|
#define EXYNOS5_GPD0(_nr) (EXYNOS5_GPIO_D0_START + (_nr))
|
|
#define EXYNOS5_GPD0(_nr) (EXYNOS5_GPIO_D0_START + (_nr))
|
|
#define EXYNOS5_GPD1(_nr) (EXYNOS5_GPIO_D1_START + (_nr))
|
|
#define EXYNOS5_GPD1(_nr) (EXYNOS5_GPIO_D1_START + (_nr))
|
|
#define EXYNOS5_GPY0(_nr) (EXYNOS5_GPIO_Y0_START + (_nr))
|
|
#define EXYNOS5_GPY0(_nr) (EXYNOS5_GPIO_Y0_START + (_nr))
|