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@@ -44,7 +44,15 @@ struct s5h1409_state {
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int if_freq;
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u32 is_qam_locked;
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- u32 qam_state;
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+
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+ /* QAM tuning state goes through the following state transitions */
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+#define QAM_STATE_UNTUNED 0
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+#define QAM_STATE_TUNING_STARTED 1
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+#define QAM_STATE_INTERLEAVE_SET 2
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+#define QAM_STATE_QAM_OPTIMIZED_L1 3
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+#define QAM_STATE_QAM_OPTIMIZED_L2 4
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+#define QAM_STATE_QAM_OPTIMIZED_L3 5
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+ u8 qam_state;
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};
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static int debug;
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@@ -347,7 +355,7 @@ static int s5h1409_softreset(struct dvb_frontend *fe)
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s5h1409_writereg(state, 0xf5, 0);
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s5h1409_writereg(state, 0xf5, 1);
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state->is_qam_locked = 0;
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- state->qam_state = 0;
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+ state->qam_state = QAM_STATE_UNTUNED;
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return 0;
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}
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@@ -474,6 +482,59 @@ static void s5h1409_set_qam_amhum_mode(struct dvb_frontend *fe)
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struct s5h1409_state *state = fe->demodulator_priv;
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u16 reg;
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+ if (state->qam_state < QAM_STATE_INTERLEAVE_SET) {
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+ /* We should not perform amhum optimization until
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+ the interleave mode has been configured */
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+ return;
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+ }
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+
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+ if (state->qam_state == QAM_STATE_QAM_OPTIMIZED_L3) {
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+ /* We've already reached the maximum optimization level, so
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+ dont bother banging on the status registers */
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+ return;
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+ }
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+
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+ /* QAM EQ lock check */
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+ reg = s5h1409_readreg(state, 0xf0);
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+
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+ if ((reg >> 13) & 0x1) {
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+ reg &= 0xff;
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+
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+ s5h1409_writereg(state, 0x96, 0x000c);
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+ if (reg < 0x68) {
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+ if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L3) {
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+ dprintk("%s() setting QAM state to OPT_L3\n",
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+ __func__);
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+ s5h1409_writereg(state, 0x93, 0x3130);
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+ s5h1409_writereg(state, 0x9e, 0x2836);
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+ state->qam_state = QAM_STATE_QAM_OPTIMIZED_L3;
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+ }
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+ } else {
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+ if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L2) {
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+ dprintk("%s() setting QAM state to OPT_L2\n",
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+ __func__);
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+ s5h1409_writereg(state, 0x93, 0x3332);
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+ s5h1409_writereg(state, 0x9e, 0x2c37);
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+ state->qam_state = QAM_STATE_QAM_OPTIMIZED_L2;
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+ }
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+ }
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+
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+ } else {
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+ if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L1) {
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+ dprintk("%s() setting QAM state to OPT_L1\n", __func__);
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+ s5h1409_writereg(state, 0x96, 0x0008);
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+ s5h1409_writereg(state, 0x93, 0x3332);
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+ s5h1409_writereg(state, 0x9e, 0x2c37);
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+ state->qam_state = QAM_STATE_QAM_OPTIMIZED_L1;
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+ }
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+ }
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+}
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+
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+static void s5h1409_set_qam_amhum_mode_legacy(struct dvb_frontend *fe)
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+{
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+ struct s5h1409_state *state = fe->demodulator_priv;
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+ u16 reg;
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+
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if (state->is_qam_locked)
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return;
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@@ -506,6 +567,46 @@ static void s5h1409_set_qam_interleave_mode(struct dvb_frontend *fe)
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struct s5h1409_state *state = fe->demodulator_priv;
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u16 reg, reg1, reg2;
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+ if (state->qam_state >= QAM_STATE_INTERLEAVE_SET) {
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+ /* We've done the optimization already */
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+ return;
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+ }
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+
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+ reg = s5h1409_readreg(state, 0xf1);
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+
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+ /* Master lock */
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+ if ((reg >> 15) & 0x1) {
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+ if (state->qam_state == QAM_STATE_UNTUNED ||
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+ state->qam_state == QAM_STATE_TUNING_STARTED) {
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+ dprintk("%s() setting QAM state to INTERLEAVE_SET\n",
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+ __func__);
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+ reg1 = s5h1409_readreg(state, 0xb2);
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+ reg2 = s5h1409_readreg(state, 0xad);
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+
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+ s5h1409_writereg(state, 0x96, 0x0020);
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+ s5h1409_writereg(state, 0xad,
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+ (((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff)));
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+ s5h1409_writereg(state, 0xab,
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+ s5h1409_readreg(state, 0xab) & 0xeffe);
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+ state->qam_state = QAM_STATE_INTERLEAVE_SET;
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+ }
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+ } else {
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+ if (state->qam_state == QAM_STATE_UNTUNED) {
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+ dprintk("%s() setting QAM state to TUNING_STARTED\n",
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+ __func__);
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+ s5h1409_writereg(state, 0x96, 0x08);
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+ s5h1409_writereg(state, 0xab,
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+ s5h1409_readreg(state, 0xab) | 0x1001);
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+ state->qam_state = QAM_STATE_TUNING_STARTED;
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+ }
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+ }
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+}
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+
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+static void s5h1409_set_qam_interleave_mode_legacy(struct dvb_frontend *fe)
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+{
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+ struct s5h1409_state *state = fe->demodulator_priv;
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+ u16 reg, reg1, reg2;
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+
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reg = s5h1409_readreg(state, 0xf1);
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/* Master lock */
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@@ -553,16 +654,24 @@ static int s5h1409_set_frontend(struct dvb_frontend *fe,
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fe->ops.i2c_gate_ctrl(fe, 0);
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}
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- /* Optimize the demod for QAM */
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- if (p->u.vsb.modulation != VSB_8) {
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- s5h1409_set_qam_amhum_mode(fe);
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- s5h1409_set_qam_interleave_mode(fe);
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- }
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-
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/* Issue a reset to the demod so it knows to resync against the
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newly tuned frequency */
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s5h1409_softreset(fe);
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+ /* Optimize the demod for QAM */
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+ if (state->current_modulation != VSB_8) {
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+ /* This almost certainly applies to all boards, but for now
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+ only do it for the HVR-1600. Once the other boards are
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+ tested, the "legacy" versions can just go away */
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+ if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
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+ s5h1409_set_qam_amhum_mode(fe);
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+ s5h1409_set_qam_interleave_mode(fe);
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+ } else {
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+ s5h1409_set_qam_amhum_mode_legacy(fe);
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+ s5h1409_set_qam_interleave_mode_legacy(fe);
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+ }
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+ }
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+
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return 0;
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}
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@@ -656,6 +765,17 @@ static int s5h1409_read_status(struct dvb_frontend *fe, fe_status_t *status)
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*status = 0;
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+ /* Optimize the demod for QAM */
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+ if (state->current_modulation != VSB_8) {
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+ /* This almost certainly applies to all boards, but for now
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+ only do it for the HVR-1600. Once the other boards are
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+ tested, the "legacy" versions can just go away */
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+ if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
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+ s5h1409_set_qam_amhum_mode(fe);
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+ s5h1409_set_qam_interleave_mode(fe);
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+ }
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+ }
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+
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/* Get the demodulator status */
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reg = s5h1409_readreg(state, 0xf1);
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if (reg & 0x1000)
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