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+/*
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+ * This file contains the routines for TLB flushing.
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+ * On machines where the MMU does not use a hash table to store virtual to
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+ * physical translations (ie, SW loaded TLBs or Book3E compilant processors,
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+ * this does -not- include 603 however which shares the implementation with
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+ * hash based processors)
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+ *
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+ * -- BenH
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+ *
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+ * Copyright 2008 Ben Herrenschmidt <benh@kernel.crashing.org>
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+ * IBM Corp.
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+ *
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+ * Derived from arch/ppc/mm/init.c:
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+ * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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+ *
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+ * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
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+ * and Cort Dougan (PReP) (cort@cs.nmt.edu)
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+ * Copyright (C) 1996 Paul Mackerras
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+ *
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+ * Derived from "arch/i386/mm/init.c"
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+ * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License
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+ * as published by the Free Software Foundation; either version
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+ * 2 of the License, or (at your option) any later version.
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+ *
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/mm.h>
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+#include <linux/init.h>
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+#include <linux/highmem.h>
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+#include <linux/pagemap.h>
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+#include <linux/preempt.h>
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+#include <linux/spinlock.h>
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+
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+#include <asm/tlbflush.h>
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+#include <asm/tlb.h>
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+
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+#include "mmu_decl.h"
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+
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+/*
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+ * Base TLB flushing operations:
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+ *
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+ * - flush_tlb_mm(mm) flushes the specified mm context TLB's
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+ * - flush_tlb_page(vma, vmaddr) flushes one page
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+ * - flush_tlb_range(vma, start, end) flushes a range of pages
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+ * - flush_tlb_kernel_range(start, end) flushes kernel pages
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+ *
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+ * - local_* variants of page and mm only apply to the current
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+ * processor
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+ */
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+
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+/*
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+ * These are the base non-SMP variants of page and mm flushing
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+ */
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+void local_flush_tlb_mm(struct mm_struct *mm)
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+{
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+ unsigned int pid;
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+
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+ preempt_disable();
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+ pid = mm->context.id;
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+ if (pid != MMU_NO_CONTEXT)
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+ _tlbil_pid(pid);
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+ preempt_enable();
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+}
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+EXPORT_SYMBOL(local_flush_tlb_mm);
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+
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+void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
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+{
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+ unsigned int pid;
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+
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+ preempt_disable();
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+ pid = vma ? vma->vm_mm->context.id : 0;
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+ if (pid != MMU_NO_CONTEXT)
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+ _tlbil_va(vmaddr, pid);
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+ preempt_enable();
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+}
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+EXPORT_SYMBOL(local_flush_tlb_page);
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+
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+
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+/*
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+ * And here are the SMP non-local implementations
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+ */
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+#ifdef CONFIG_SMP
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+
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+static DEFINE_SPINLOCK(tlbivax_lock);
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+
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+struct tlb_flush_param {
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+ unsigned long addr;
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+ unsigned int pid;
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+};
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+
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+static void do_flush_tlb_mm_ipi(void *param)
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+{
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+ struct tlb_flush_param *p = param;
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+
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+ _tlbil_pid(p ? p->pid : 0);
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+}
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+
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+static void do_flush_tlb_page_ipi(void *param)
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+{
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+ struct tlb_flush_param *p = param;
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+
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+ _tlbil_va(p->addr, p->pid);
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+}
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+
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+
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+/* Note on invalidations and PID:
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+ *
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+ * We snapshot the PID with preempt disabled. At this point, it can still
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+ * change either because:
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+ * - our context is being stolen (PID -> NO_CONTEXT) on another CPU
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+ * - we are invaliating some target that isn't currently running here
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+ * and is concurrently acquiring a new PID on another CPU
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+ * - some other CPU is re-acquiring a lost PID for this mm
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+ * etc...
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+ *
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+ * However, this shouldn't be a problem as we only guarantee
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+ * invalidation of TLB entries present prior to this call, so we
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+ * don't care about the PID changing, and invalidating a stale PID
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+ * is generally harmless.
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+ */
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+
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+void flush_tlb_mm(struct mm_struct *mm)
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+{
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+ cpumask_t cpu_mask;
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+ unsigned int pid;
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+
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+ preempt_disable();
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+ pid = mm->context.id;
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+ if (unlikely(pid == MMU_NO_CONTEXT))
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+ goto no_context;
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+ cpu_mask = mm->cpu_vm_mask;
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+ cpu_clear(smp_processor_id(), cpu_mask);
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+ if (!cpus_empty(cpu_mask)) {
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+ struct tlb_flush_param p = { .pid = pid };
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+ smp_call_function_mask(cpu_mask, do_flush_tlb_mm_ipi, &p, 1);
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+ }
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+ _tlbil_pid(pid);
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+ no_context:
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+ preempt_enable();
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+}
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+EXPORT_SYMBOL(flush_tlb_mm);
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+
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+void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
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+{
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+ cpumask_t cpu_mask;
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+ unsigned int pid;
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+
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+ preempt_disable();
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+ pid = vma ? vma->vm_mm->context.id : 0;
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+ if (unlikely(pid == MMU_NO_CONTEXT))
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+ goto bail;
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+ cpu_mask = vma->vm_mm->cpu_vm_mask;
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+ cpu_clear(smp_processor_id(), cpu_mask);
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+ if (!cpus_empty(cpu_mask)) {
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+ /* If broadcast tlbivax is supported, use it */
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+ if (mmu_has_feature(MMU_FTR_USE_TLBIVAX_BCAST)) {
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+ int lock = mmu_has_feature(MMU_FTR_LOCK_BCAST_INVAL);
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+ if (lock)
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+ spin_lock(&tlbivax_lock);
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+ _tlbivax_bcast(vmaddr, pid);
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+ if (lock)
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+ spin_unlock(&tlbivax_lock);
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+ goto bail;
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+ } else {
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+ struct tlb_flush_param p = { .pid = pid, .addr = vmaddr };
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+ smp_call_function_mask(cpu_mask,
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+ do_flush_tlb_page_ipi, &p, 1);
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+ }
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+ }
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+ _tlbil_va(vmaddr, pid);
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+ bail:
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+ preempt_enable();
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+}
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+EXPORT_SYMBOL(flush_tlb_page);
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+
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+#endif /* CONFIG_SMP */
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+
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+/*
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+ * Flush kernel TLB entries in the given range
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+ */
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+void flush_tlb_kernel_range(unsigned long start, unsigned long end)
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+{
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+#ifdef CONFIG_SMP
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+ preempt_disable();
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+ smp_call_function(do_flush_tlb_mm_ipi, NULL, 1);
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+ _tlbil_pid(0);
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+ preempt_enable();
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+#endif
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+ _tlbil_pid(0);
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+}
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+EXPORT_SYMBOL(flush_tlb_kernel_range);
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+
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+/*
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+ * Currently, for range flushing, we just do a full mm flush. This should
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+ * be optimized based on a threshold on the size of the range, since
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+ * some implementation can stack multiple tlbivax before a tlbsync but
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+ * for now, we keep it that way
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+ */
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+void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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+ unsigned long end)
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+
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+{
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+ flush_tlb_mm(vma->vm_mm);
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+}
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+EXPORT_SYMBOL(flush_tlb_range);
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Benjamin Herrenschmidt