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@@ -174,7 +174,7 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
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#define SPI_IMX2_3_CTRL 0x08
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#define SPI_IMX2_3_CTRL_ENABLE (1 << 0)
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#define SPI_IMX2_3_CTRL_XCH (1 << 2)
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-#define SPI_IMX2_3_CTRL_MODE(cs) (1 << ((cs) + 4))
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+#define SPI_IMX2_3_CTRL_MODE_MASK (0xf << 4)
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#define SPI_IMX2_3_CTRL_POSTDIV_OFFSET 8
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#define SPI_IMX2_3_CTRL_PREDIV_OFFSET 12
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#define SPI_IMX2_3_CTRL_CS(cs) ((cs) << 18)
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@@ -253,8 +253,14 @@ static int __maybe_unused spi_imx2_3_config(struct spi_imx_data *spi_imx,
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{
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u32 ctrl = SPI_IMX2_3_CTRL_ENABLE, cfg = 0;
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- /* set master mode */
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- ctrl |= SPI_IMX2_3_CTRL_MODE(config->cs);
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+ /*
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+ * The hardware seems to have a race condition when changing modes. The
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+ * current assumption is that the selection of the channel arrives
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+ * earlier in the hardware than the mode bits when they are written at
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+ * the same time.
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+ * So set master mode for all channels as we do not support slave mode.
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+ */
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+ ctrl |= SPI_IMX2_3_CTRL_MODE_MASK;
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/* set clock speed */
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ctrl |= spi_imx2_3_clkdiv(spi_imx->spi_clk, config->speed_hz);
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